Features/OptionsGeneral DescriptionTable of ContentsTable4: Pin Descriptions (54-pin TSOP)Table 5: Ball Descriptions (54-Ball FBGA)Table 6: Ball Descriptions (60-ball FBGA)Functional DescriptionInitializationRegister DefinitionMode RegisterBurst LengthBurst TypeCAS LatencyOperating ModeWrite Burst ModeCommandsCOMMAND INHIBITNO OPERATION (NOP)LOAD MODE REGISTERACTIVEREADWRITEPRECHARGEAUTO PRECHARGEBURST TERMINATEAUTO REFRESHSELF REFRESHOperationBank/Row ActivationREADsWRITEsPRECHARGEPower-DownCLOCK SUSPENDBURST READ/SINGLE WRITECONCURRENT AUTO PRECHARGEAbsolute Maximum RatingsNotesFigure 53: 54-PIN PLASTIC TSOP (400 mil)Figure 54: FBGA “FB” Package, 60-Ball, 8mm x 16mm x4, x8Figure 55: FBGA “FG” Package, 54-ball, 8mm x 14mm x16PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.109005aef8091e6a8 Micron Technology, Inc., reserves the right to change products or specifications without notice.256MSDRAM_G.p65 – Rev. G; Pub. 9/03 ©2003 Micron Technology, Inc.256Mb: x4, x8, x16SDRAMTable 2: Key Timing ParametersSPEED CLOCK ACCESS TIME SETUP HOLDGRADE FREQUENCY CL = 2* CL = 3* TIME TIME-7E 143 MHz – 5.4ns 1.5ns 0.8ns-75 133 MHz – 5.4ns 1.5ns 0.8ns-7E 133 MHz 5.4ns – 1.5ns 0.8ns-75 100 MHz 6ns – 1.5ns 0.8ns64 Meg x 4 32 Meg x 8 16 Meg x 16Configuration 16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banksRefresh Count 8K 8K 8KRow Addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12)Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)Column Addressing 2K (A0–A9, A11) 1K (A0–A9) 512 (A0–A8)SYNCHRONOUSDRAMMT48LC64M4A2 – 16 Meg x 4 x 4 banksMT48LC32M8A2 – 8 Meg x 8 x 4 banksMT48LC16M16A2 – 4 Meg x 16 x 4 banksFor the latest data sheet, please refer to the Micron Web site:www.micron.com/dramdsFigure 1: Pin Assignment (Top View)54-Pin TSOPFeatures• PC66-, PC100-, and PC133-compliant• Fully synchronous; all signals registered onpositive edge of system clock• Internal pipelined operation; column address canbe changed every clock cycle• Internal banks for hiding row access/precharge• Programmable burst lengths: 1, 2, 4, 8, or full page• Auto Precharge, includes CONCURRENT AUTOPRECHARGE, and Auto Refresh Modes• Self Refresh Mode• 64ms, 8,192-cycle refresh• LVTTL-compatible inputs and outputs• Single +3.3V ±0.3V power supplyOptions Marking• Configurations64 Meg x 4 (16 Meg x 4 x 4 banks) 64M432 Meg x 8 ( 8 Meg x 8 x 4 banks) 32M816 Meg x 16 ( 4 Meg x 16 x 4 banks) 16M16• WRITE Recovery (tWR)tWR = “2 CLK”1A2• Package/Pinout54-pin TSOP II OCPL2 (400 mil) (standard) TG54-pin TSOP II OCPL2 (400 mil) (lead-free) P60-ball FBGA (x4, x8) FB4, 554-ball FBGA (x16) FG360-ball FBGA (x4, x8) (lead-free) BB4, 554-ball FBGA (x16) (lead-free) BG3• Timing (Cycle Time)7.5ns @ CL = 2 (PC133) -7E7.5ns @ CL = 3 (PC133) -75• Self RefreshStandard NoneLow power L3• Operating TemperatureCommercial (0oC to +70oC) NoneIndustrial (-40oC to +85oC) IT3NOTE: 1. Refer to Micron Technical Note TN-48-05.2. Off-center parting line.3. Consult Micron for availability.4. Not available in x16 configuration.5. Actual FBGA part marking shown on page 60.Note: The # symbol indicates signal is active LOW. A dash (–)indicates x8 and x4 pin function is same as x16 pin function.VDDDQ0VDDQDQ1DQ2VssQDQ3DQ4VDDQDQ5DQ6VssQDQ7VDDDQMLWE#CAS#RAS#CS#BA0BA1A10A0A1A2A3VDD123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928VssDQ15VssQDQ14DQ13VDDQDQ12DQ11VssQDQ10DQ9VDDQDQ8VssNCDQMHCLKCKEA12A11A9A8A7A6A5A4Vssx8x16 x16x8 x4x4- DQ0- NCDQ1- NCDQ2- NCDQ3- NC- NC- - - - - - - - - - - - - NC- NCDQ0- NCNC- NCDQ1- NC- NC- - - - - - - - - - - - - DQ7- NCDQ6- NCDQ5- NCDQ4- NC- - DQM- - - - - - - - - - - - NC- NCDQ3- NCNC- NCDQ2- NC- - DQM- - - - - - - - - - - *CL = CAS (READ) latencyPart Number Example:MT48LC16M16A2TG-75 Table 1: Address Table2256Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.256MSDRAM_G.p65 – Rev. G; Pub. 9/03 ©2003, Micron Technology, Inc.256Mb: x4, x8, x16SDRAMFigure 2: 60-Ball FBGA Assignment (Top View)64 Meg x 4 SDRAM8mm x 16mm “FB”32 Meg x 8 SDRAM 8mm x 16mm “FB”NOTE: FBGA pin Symbol, Type, and Descriptions are identical to the listing of the 54-pin TSOP table on page 9.ABCDEFGHJKLMNPR12345678Depopulated BallsNCVssNCVssQVDDQDQ3NCNCNCVssQVDDQDQ2NCNCNCVssNCDQMNCCKA12CKEA11A9A8A7A6A5A4VssVDDNCVDDQNCDQ0VssQNCNCVDDQNCDQ1VssQNCNCVDDNCWE#CAS#RAS#NCNCCS#BA1BA0A0A10A2A1VDDA3ABCDEFGHJKLMNPR12345678Depopulated BallsDQ7VssNCVssQVDDQDQ6DQ5NCNCVssQVDDQDQ4NCNCNCVssNCDQMNCCKA12CKEA11A9A8A7A6A5A4VssVDDDQ0VDDQNCDQ1VssQNCDQ2VDDQNCDQ3VssQNCNCVDDNCWE#CAS#RAS#NCNCCS#BA1BA0A0A10A2A1VDDA33256Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.256MSDRAM_G.p65 – Rev. G; Pub. 9/03 ©2003, Micron Technology, Inc.256Mb: x4, x8, x16SDRAMFigure 3: 54-Ball FBGA Assignment (Top View)16 Meg x 16 SDRAM8mm x 14mm “FG”ABCDEFGHJ123456789Depopulated BallsVssDQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8NCUDQMCLKA12A11A8A7VssA5VSSQVDDQVSSQVDDQVssCKEA9A6A4VDDQVssQVDDQVSSQVDDCAS#BA0A0A3DQ0VDDDQ2DQ1DQ4DQ3DQ6DQ5LDQMDQ7RAS#WE#BA1CS#A1A10A2VDD4256Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.256MSDRAM_G.p65 – Rev. G; Pub. 9/03 ©2003, Micron Technology, Inc.256Mb: x4, x8, x16SDRAMGeneral DescriptionThe 256Mb SDRAM is a high-speed CMOS,dynamic random-access memory containing268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signalsare registered on the positive edge of the clock signal,CLK). Each of the x4’s 67,108,864-bit banks is orga-nized as 8,192 rows by 2,048 columns by4 bits. Each of the x8’s 67,108,864-bit banks is orga-nized as 8,192 rows by 1,024 columns by 8 bits. Each ofthe x16’s 67,108,864-bit banks is organized as 8,192rows by 512 columns by 16 bits.Read and write accesses to the SDRAM are burstoriented; accesses start at a selected location and con-tinue for a programmed number of locations in a pro-grammed sequence. Accesses begin with the registra-tion of an ACTIVE command, which is then followed bya READ or WRITE command. The address bits regis-tered coincident with the ACTIVE command are usedPART NUMBER ARCHITECTURE PACKAGEMT48LC64M4A2TG 64 Meg x 4 54-pin TSOP IIMT48LC64M4A2P 64 Meg x 4 54-pin TSOP IIMT48LC64M4A2FB*
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