1.0 Motivation2.0 Introduction3.0 Prelab4.0 Lab Procedure4.1 Lab2Top4.2 Behavioral Accumulator4.3 Structural Peak Detector4.3.1 Structural Register4.3.2 Structural Comparator4.3.3 Structural Peak Detector 5.0 Lab 2 CheckoffEECS 150 Spring 2006 Lab 2 UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE ASSIGNED: Week of 1/30 DUE: Week of 2/6, 10 minutes after start of your assigned lab section. Lab 2 Designing with Verilog 1.0 Motivation In this lab you will learn how to express a circuit design in a Hardware Description Language (HDL), namely Verilog. By creating two similar designs in behavioral and structural verilog, you will get a chance to not only familiarize yourself with different styles of Verilog, but also with the ModelSim simulator. 2.0 Introduction To support the creation of very efficient circuits, and as an effort to ease entry of old designs, and importing designs from other environments, Verilog supports the use of universally accessible primitive gates like and, or and not. In addition, it supports dataflow and behavioral modeling, which allow the design of more efficient control. In this lab, you will investigate the use of the two primary kinds of Verilog: structural and behavioral. You will create two similar, simple modules. One module will be specified in behavioral Verilog, where you will describe the function of the circuit succinctly and rely on the modeling and synthesis CAD tools to determine the exact circuit. The other circuit will be written in structural Verilog, were you will describe the circuit down to the gate level. The final piece of Verilog in this lab will be the testbench, which, though also written in behavioral Verilog, is a little different in that it cannot be synthesized. This is because it describes an artificial set of test stimulus rather than an actual circuit. 3.0 Prelab Please make sure to complete the prelab before you attend your lab section. You will not be able to finish this lab in 3 hrs otherwise! 1. Read this handout thoroughly. Pay particular attention to Section 4.0 Lab Procedure as it describes in detail the circuits you must create. 2. Examine the Verilog provided for this week’s lab. a. Make sure you understand exactly how the Lab2Testbench works. 3. Write all of your Verilog ahead of time. a. You should add more test cases to Lab2Testbench.v. You will not get checked off for this lab without a more thorough testing of your modules. 4. You will need the entire 3 hr lab to test and debug your Verilog! UCB 1 2006EECS 150 Spring 2006 Lab 2 4.0 Lab Procedure Since we expect you to write your Verilog ahead of time, and Verilog is nothing more than a bunch of standard text in a file with a *.v extension, you can do this part of the lab entirely from home in your favorite text editor (we recommend notepad). Or you can come into the lab and use the tools there. For those of you who like maintaining a single Xilinx Project Navigator project for each lab, you can even create the project ahead of time and write your Verilog from within Project Navigator. Whatever editor you use to create your Verilog files, at some point you will need to add all of the Verilog files (including Lab2Top and Lab2Testbench) to a new Xilinx Project Navigator project, or to a new ModelSim project, to test your code and get it checked off. Remember to manage your Verilog, projects and folders well. Doing a poor job of managing your files can cost you hours of rewriting code, if you accidentally delete your files. 4.1 Lab2Top In this lab you will be building the two sub-modules of Lab2Top. Lab2Top takes a string of 8-bit inputs and maintains both a running sum of the inputs using an Accumulator and the largest of the inputs using a PeakDetector. The PeakSelect input to Lab2Top can be used to select which of these values appears at the output Out. Below are: a high-level block diagram of Lab2Top, a table specifying its ports and their purposes and a hierarchy of the modules that you will need to build to complete this lab. Lab2Top Figure 1: Lab2Top High Level Block Diagram Signal Width Dir Description In 8 I The input value Out 8 O The output value from either the PeakDetector or AccumulatorUCB 2 2006EECS 150 Spring 2006 Lab 2 Enable 1 I Notify Lab2Top to accept the current input at InPeakSelect 1 I Selects the output form the PeakDetector when 1’b1Clock 1 I The Clock signal Reset 1 I Reset both the Accumulator and the PeakDetectorTable 1: Port Specification for Lab2Top Lab2Top Figure 2: Hierarchy of Modules 4.2 Behavioral Accumulator Figure 3: The Accumulator UCB 3 2006EECS 150 Spring 2006 Lab 2 1. In the text editor of your choice (we recommend notepad) create a file called Accumulator.v in which you will define a single module called Accumulator. a. This module should have the ports listed in Table 2. b. Be sure to use good Verilog style. You’ll be graded on this! Signal Width Dir Description In 8 I The input value to be added to the total output Out 8 O The sum of all previous input values Enable 1 I Notify the accumulator to add In to Out Clock 1 I The Clock signal, the output changes only on rising edges Reset 1 I Reset the output to 8’h00. Table 2: Port Specification for Accumulator 2. Specify your module entirely in behavioral Verilog. a. Our solution takes 4 lines of behavioral Verilog (not counting declarations). b. You may not instantiate any other module within your accumulator. c. You may wish to refer to the lab lecture slides for examples of behavioral Verilog. 3. Types of Assignment a. A blocking assignment is written as “=” and should be used in combinational logic. b. A non-blocking assignment is written as“<=” and should be used for sequential logic, namely anywhere you have an always @ (posedge Clock) c. Note that these kinds of assignments refer only to always blocks. The assign keyword always requires a simple “=”. 4. Reg vs. Register a. The keyword reg in Verilog names a location into which an always block can place a value. It does not create any kind of register, it is merely a poorly named artifact of days past. b. always @ (posedge Clock) implies a register. i. Any reg assigned using Non-blocking assignment (<=) in an always @ (posedge Clock) block will become a register during synthesis. 5. Test this module individually a. You should be able to modify the
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