Understanding Engineers #1Understanding Engineers #2Midterm IISequential Logic ImplementationSDRAM Memory ControllerTwo-way Video Conferencing ProjectVideoconferencing System ConceptComputer OrganizationRegister TransferSlide 10State Machine ImplementationTime State (Divide & Conquer)Jump CountersSlide 14Slide 15Branch SequencersSlide 17Vertical MicroprogrammingVertical ProgrammingDesign/Reverse EngineeringCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 1Understanding Engineers #1The graduate with a Science degree asks, "Why does it work?"The graduate with an Engineering degree asks, "How does it work?"The graduate with an Accounting degree asks, "How much will it cost?"The graduate with an Arts degree asks, "Do you want fries with that?"CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 2Understanding Engineers #2MS CS -- Soft-wareMS EE -- Hard-wareMBA -- Un-a-wareMFA -- No-wareCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 3Midterm IITHIS Thursday, 22 March (that is TWO days from today!), 2:10 -- 3:30+, CS 150 LabLectures 10, 11, 12, (no lecture 13!), 14, 15, 16; Labs #4 and #5 (Debugging/Logic Analyzers) + Checkpoints #0 and #1 (SDRAM + Video Encoder)Don’t forget: Spring 05/Fall 05 exams are on-line!5 x 10 point questions, mostly design-orientedClosed book, open crib sheet; PENCIL, not pen!Two review sessions: Tu 8 PM and W 8 PM in the labNOTE: Discussion sections and lab lecture cancelled this weekCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 4Sequential Logic ImplementationModels for representing sequential circuitsMealy, Moore, and synchronous Mealy machinesVerilog specifications for state machinesFinite state machine design procedureDeriving state diagram from word specificationsDeriving state transition tableDetermining next state and output functionsImplementing combinational logicCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 5SDRAM Memory ControllerStatic RAM Technology6T Memory CellMemory Access TimingDynamic RAM Technology1T Memory CellMemory Access TimingTheory in lecture, but practical detailed memory system organization and timing in Lab Checkpoint #0CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 6Two-way Video Conferencing ProjectProject Concept and BackgroundSDRAM Controller (Checkpoint #0)Video Encoder/Display System (Checkpoint #1)CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 7Videoconferencing System ConceptDisplayVideo EncoderVideo Encoder(Checkpoint #1)Video DecoderCameraVideostreamVid eoDecod erCheckpoint #2Checkpoint #4SDRAM(Checkpoint #0)Multiport SDRAMMemory SystemMultiportArbitrationWireless Transceiver(Checkpoint #3)CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 8Computer OrganizationComputer design as an application of digital logic design proceduresComputer = processing unit + memory systemProcessing unit = control + datapathControl = finite state machineInputs = machine instruction, datapath conditionsOutputs = register transfer control signals, ALU operation codesInstruction interpretation = instruction fetch, decode, executeDatapath = functional units + registersFunctional units = ALU, multipliers, dividers, etc.Registers = program counter, shifters, storage registersCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 9Register TransferLdCASel0BSel1DECSel01C A Sel 0; Ld 1C B Sel 1; Ld 1ClkSelLdClkA on BusLd Cfrom BusBusB on Bus?CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 10Register TransferPoint-to-point connectionDedicated wiresMuxes on inputs ofeach registerCommon input from multiplexerLoad enablesfor each registerControl signalsfor multiplexerCommon bus with output enablesOutput enables and loadenables for each registerrtMUXrsMUXrdMUXR4MUXrsMUXrt rd R4BUSrs rt rd R4CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 11State Machine ImplementationAlternative controller FSM implementation approaches based on:Classical Moore and Mealy machinesTime state: Divide and CounterJump countersMicroprogramming (ROM) based approachesbranch sequencershorizontal microcodevertical microcodeCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 12Time State (Divide & Conquer)Time State FSMMost instructions follow same basic sequenceDiffer only in detailed execution sequenceTime State FSM can be parameterized by opcode and AC statesInstruction State:stored in IR<15:14>Condition State:stored in AC<15>T0T1T2T3T4T5T6T7Wait/Wait/Wait/Wait/Wait/Wait/BRN • AC 0/(LD + ST + ADD) • Wait/BRN + (ST • Wait)/(LD + ADD) • WaitIR=11=10=01=00LD STADD BRNAC<15>=0AC<15>=1AC ? 0AC < 0CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 13Jump CountersPure Jump CounterLogic blocks implemented via discrete logic, PLAs, ROMsNOTE: No inputs tojump state logicInputsCount, Load, Clear LogicJump State LogicSynchronous Counter State RegisterClearLoadCountCLOCKCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 14Jump CountersHybrid Jump CounterLoad inputs arefunction of stateand FSM inputsInputsCount, Load, Clear LogicJump State LogicClearLoadCountSynchronous Counter State RegisterCLOCKCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 15Jump CountersCLR, CNT, LDimplemented via Mux LogicActive Lo outputs:hi input inverted atthe outputNote that CNT isactive hi on counterso invert MUX inputs!CLR = CLRm + ResetCLR = CLRm + Reset/CLR++ +163154150150150/CLRm/Reset/CLRCNTJump StateIR<15>IR14IR15IR<14>3 2 1 0P TCLKD C B ARCOQD QC QB QALOADCLR/LDResetWait/Reset/Wait1 01 0G2 G1D C B AWait/WaitEOUTEOUT EOUT/WaitCNT10/CLRm /LD1514131211109876543210\S13\S12\S11\S10\S9\S8\S7\S6\S5\S4\S3\S2\S1\S0E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1E0GS3 S2 S1 S0E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1E0GS3 S2 S1 S0E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1E0GS3 S2 S1 S0CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 16Branch Sequencers4 Way Branch SequencerCurrent State selects two inputs to form part of ROM addressThese select one of four possible next states (and output sets)Every state has exactly four possible next statesMuxMuxI n p u t s64 Word ROMstatex11 x10 x01 x00Z Y X WC o n t r o lS i g n a l sa0 a1a2 a3a4a5NW XYZCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 17Branch SequencersAlternativeHorizontalImplementationInput MUX controlled by encoded signals,
View Full Document