1Fall 2011 EECS150 Lecture 1Page 1EECS150 - Digital DesignLecture 1 - IntroductionAugust 25, 2011Elad AlonElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www-inst.eecs.berkeley.edu/~cs150Fall 2011 EECS150 Lecture 1Page 2What This Class is All About• Designing, optimizing, and realizing synchronous digital systems– Both critical components and design techniques• What you will learn:– Importance of making things work– Using abstraction to deal with complexity• And to use the “right” abstraction for the problem you are solving– What specifications are important in digital systems• And how they trade off with each other2Fall 2011 EECS150 Lecture 1Page 3Where This Is UsefulConsumerProductsCommunicationsInfrastructureAutomotiveAerospace and MilitaryFall 2011 EECS150 Lecture 1Page 4Course ContentIC processingTransistor PhysicsDevicesCircuitsEE 40CS 61CGatesFlipFlopsHDLMachine OrganizationInstruction Set ArchProgramming Languages Asm / Machine LangDeep Digital Design ExperienceFundamentals of Boolean LogicSynchronous CircuitsFinite State MachinesTiming & ClockingDevice Technology & ImplicationsController DesignArithmetic UnitsEncoding, FramingTesting, DebuggingHardware ArchitectureHardware Design Language (HDL) Design Flow (CAD)3Fall 2011 EECS150 Lecture 1Page 5Course Content - Design LayersNot a course on transistor physics and transistor circuits. Although, we will look at these to better understand the primitive elements for digital circuits. High-level Organization : Hardware ArchitecturesSystem Building Blocks : Arithmetic units, controllersCircuit Elements : Memories, logic blocksTransistor-level circuit implementationsCircuit primitives : Transistors, wiresNot a course on computer architecture or the architecture of other systems. Although we will look at these as examples. Fall 2011 EECS150 Lecture 1Page 6Practical Information• Instructor: – Professor Elad Alon• 519 Cory Hall, 642-0237, [email protected]• Office hours: Tu./Th. 11am-12pm• TA’s:– Daiwei Li, [email protected]• Office hours: Tues. 4-5pm, 125 Cory– James Parker, [email protected]• Office hours: Mon. 2-3pm, 125 Cory– Dan Yeager, [email protected]• Office hours: Wed. 4-5pm, 125 Cory• Webpage: http://www-inst.eecs.berkeley.edu/~cs1504Fall 2011 EECS150 Lecture 1Page 7Enrollment• Working on getting a larger room• When/if this happens should be able to accommodate everyone on the waiting list• Some important points:• This class will not be easy• Workload will be heavy• Definitely not the class for you if looking for an easy grade• But, you will learn a lot• Class will be videotaped/webcast• But please don’t skip the lectures Fall 2011 EECS150 Lecture 1Page 8Discussions• Two discussion sessions (125 Cory)• Fri. 2-3pm• Mon. 11am-12pm• Identical material in both sessions• No discussions this week• First discussion will be held on Fri. Sept. 2nd2-3pm5Fall 2011 EECS150 Lecture 1Page 9Labs• Schedule/staffing (125 Cory):• Tues. 5-8pm: Daiwei, James• Wed. 9am-12pm: Dan, Daiwei• Wed. 5-8pm: James, Dan• Pick one lab and stick with it• No“lablecture”onFridays, 2-3pm.• No lab sections this week; labs start next week•(1stlab Tues. Aug. 30th)Fall 2011 EECS150 Lecture 1Page 10Assignments• 9 homeworks• 5 labs• Can work together on these• But must turn in your own solution• Design project (split into multiple phases)• Done in pairs – find a partner now!• 1 midterm, 1 final• Midterm: Thurs. Oct. 27th, evening (TBD)• Final: Tues. Dec. 13th, 8-11am6Fall 2011 EECS150 Lecture 1Page 11Course Grading• Homeworks: 10%• Labs: 5%• Midterm: 20%• Final: 25%• Project: 40%• Homeworks due Thursdays 5pm• Labs due beginning of next lab session• Project checkoffs due no later than Wed. 8pm• Will probably have sign-up sheets for check-offs during lab times Fall 2011 EECS150 Lecture 1Page 12A Couple of Notes• No late assignments will be accepted• Homeworks, labs, and project checkpoints are crucial for you to understand the material• We promise to minimize busy-work• Course is fast-paced – you will not have time to catch up• Don’t even think about cheating• We have software that automatically compares submissions• Penalties for cheating will be stiff – see website for policy• If you’re not here to learn, this isn’t the class for you7Fall 2011 EECS150 Lecture 1Page 13A Few More Tips• Attend lectures and office hours, ask questions• Helps to make sure you understand the material and can apply it in new situations• Be well organized and neat in all of your written submissions• In lab/project, add complexity one step at a time• Always have a working design• Planning is crucial• But don’t be afraid to abandon your original plan and start over if it becomes clear it won’t workFall 2011 EECS150 Lecture 1Page 14Course Materials• Class notes, homework & lab assignments,solutions, and other documentation will beavailable on the class webpage: http://www-inst.eecs.berkeley.edu/~cs150– Check the class webpage and newsgroupoften! – You are responsible for checking the classwebpage at least once every 24 hours (in case we need to post changes/corrections.]Textbook: Harris & HarrisPublisher: Morgan Kaufmannpiazza For online Q/A. http://www.piazzza.com/More info later.8Fall 2011 EECS150 Lecture 1Page 15Evolution of Digital Design As Evidenced by CS150• Final project circa 1980:– Example project: pong game with buttons for paddle and LEDs for output.– Few 10’s of logic gates– Gates hand-wired together on “bread-board” (protoboard).– No computer-aided design tools– Debugged with oscilloscope and logic analyzerFall 2011 EECS150 Lecture 1Page 16CS150 ca. 1995• Final project:– Example project: MIDI music synthesizer– Few 1000’s of logic gates– Gates wired together internally on field programmable gate array (FPGA) development board with some external components.– Circuit designed “by-hand”, computer-aided design tools to help map the design to the hardware.– Debugged with circuit simulation, oscilloscope and logic analyzer9Fall 2011 EECS150 Lecture 1Page 17CS150 ca. 2000• Final project:– Ex: eTV – decode and display streaming video over Ethernet– Few 10,000’s of logic gates– Gates wired together internally on FPGA development board and communicate with standard external components.–
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