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Berkeley COMPSCI 150 - Lecture 10 - Combinational Logic Circuits Part 1

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EECS150 - Digital Design Lecture 10 - Combinational Logic Circuits Part 1Combinational Logic (CL) DefinedAddersCarry-ripple AdderSubtractorsAdders (cont.)Carry Select AdderSlide 8Slide 9Carry Look-ahead AddersSlide 11Slide 12Slide 13Slide 14Slide 15Adders in FPGAsSpring 2002 EECS150 - Lec10-cl1Page 1EECS150 - Digital DesignLecture 10 - Combinational Logic Circuits Part 1Feburary 26, 2002John WawrzynekSpring 2002 EECS150 - Lec10-cl1Page 2Combinational Logic (CL) Definedyi = fi(x0 , . . . . , xn-1), where x, y are {0,1}. Y is a function of only X. •If we change X, Y will change immediately (well almost!). •There is an implementation dependent delay from X to Y.Spring 2002 EECS150 - Lec10-cl1Page 3AddersFull-adder cell (FA) revisited:F Aa b c i nc o u t sa b c i n c o u t s0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 10 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00101a b a bc i n c i nc o u t sSpring 2002 EECS150 - Lec10-cl1Page 4Carry-ripple Adder•Each cell:ri = ai XOR bi XOR cincout = aicin + aibi + bicin = cin(ai + bi) + aibi•4-bit adder:•What about subtraction?“Full adder cell”Spring 2002 EECS150 - Lec10-cl1Page 5SubtractorsA - B = A + (-B)How do we form -B?1. complement B 2. add 1S U Bs 0s 1s n - 1b n - 1 b 1 b 0a n - 1 a 1 a 0c o u t c i nn - b i t a d d e rSpring 2002 EECS150 - Lec10-cl1Page 6Adders (cont.)Ripple AdderRipple adder is inherently slow because, in generals7 must wait for c7 which must wait for c6 …T  n, Cost  nHow do we make it faster, perhaps with more cost?F Ac 0a 0b 0s 0c 1c 2c 3c 4c 5c 6c 7s 7 s 6Spring 2002 EECS150 - Lec10-cl1Page 7Carry Select AdderF Ac 0a 0b 0s 0F A1 0 1 01 0 1 001c 810a 1a 2a 3a 4a 5a 6a 7a 4a 5a 6a 7b 7 b 6 b 5 b 4 b 3b 7 b 6 b 5 b 4b 2 b 1s 1s 2s 3s 4s 5s 6s 7T = Tripple_adder / 2 + TMUXCOST = 1.5 * COSTripple_adder+ (n+1) * COSTMUXSpring 2002 EECS150 - Lec10-cl1Page 8Carry Select Adder•Extending Carry-select to multiple blocks•What is the optimal # of blocks and # of bits/block?–If # blocks too large delay dominated by total mux delay–If # blocks too small delay dominated by adder delay101 0 1 0 1 0 1 04 - b i t A d d e r 4 - b i tA d d e r101 0 1 0 1 0 1 04 - b i t A d d e r 4 - b i tA d d e r101 0 1 0 1 0 1 04 - b i t A d d e r 4 - b i tA d d e r4 - b i t A d d e ra 3 - a 0b 3 - b 0c i nc o u ta 1 1 - a 8b 1 1 - b 8a 1 5 - a 1 2b 1 5 - b 1 2 b 7 - b 4 a 7 - a 4bits N of stages NT  sqrt(N),Cost 2*ripple + muxesSpring 2002 EECS150 - Lec10-cl1Page 9Carry Select Adder•Ttotal = sqrt(N) TFA–assuming TFA = TMUX•For ripple adder Ttotal = N TFA•Is sqrt(N) really the optimum?–From right to left increase size of each block to better match delays–Ex: 64-bit adder, use block sizes [13 12 11 10 9 8 7]•How about recursively defined carry select?101 0 1 0 1 0 1 04 - b i t A d d e r 4 - b i tA d d e r101 0 1 0 1 0 1 04 - b i t A d d e r 4 - b i tA d d e r101 0 1 0 1 0 1 04 - b i t A d d e r 4 - b i tA d d e r4 - b i t A d d e ra 3 - a 0b 3 - b 0c i nc o u ta 1 1 - a 8b 1 1 - b 8a 1 5 - a 1 2b 1 5 - b 1 2 b 7 - b 4 a 7 - a 4Spring 2002 EECS150 - Lec10-cl1Page 10Carry Look-ahead Adders•In general, for n-bit addition best we can achieve is delay  log(n)•How do we arrange this? (think trees)•First, reformulate basic adder stage:carry “kill” ki = ai’ bi’carry “propagate” pi = ai  bicarry “generate” gi = ai bici+1 = gi + picisi = pi  ci0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1a b ci ci+1 sSpring 2002 EECS150 - Lec10-cl1Page 11Carry Look-ahead Adders•Ripple adder using p and g signals:•So far, no advantage over ripple adder: T  Np0g0s0 = p0  c0c1 = g0 + p0c0s0a0b0p1g1s0 = p1  c1c2 = g1 + p1c1s1a1b1p2g2s2 = p2  c2c3 = g2 + p2c2s2a2b2p3g3s3 = p3  c3c4 = g3 + p3c3s3a3b3c0c4Spring 2002 EECS150 - Lec10-cl1Page 12Carry Look-ahead Adders•Expand carries:c0 c1 = g0 + p0 c0c2 = g1 + p1c1 = g1 + p1g0 + p1p0c0c3 = g2 + p2c2 = g2 + p2g1 + p1p2g0 + p2p1p0c0c4 = g3 + p3c3 = g3 + p3g2 + p3p2g1 + . . ....•Why not implement these equations directly to avoid ripple delay?–Lots of gates. Redundancies (full tree for each).–Gate with high # of inputs.•Let’s reorganize the equations.Spring 2002 EECS150 - Lec10-cl1Page 13Carry Look-ahead Adders•“Group” propagate and generate signals:•P true if the group as a whole propagates a carry to cout•G true if the group as a whole generates a carry•Group P and G can be generated hierarchically.pigipi+1gi+1pi+kgi+kP = pi pi+1 … pi+kG = gi+k + pi+kgi+k-1 + … + (pi+1pi+2 … pi+k)gicincoutCout = G + PCinSpring 2002 EECS150 - Lec10-cl1Page 14Carry Look-ahead Addersa0b0a1b1a2b2aa3b3a4b4a5b5bc3 = Ga + Pac0PaGaPbGba6b6a7b7a8b8cc6 = Gb + Pbc3PcGcP = PaPbPcG = Gc + PcGb + PbPcGac9 = G + Pc0c09-bit Example of hierarchically generated P and G signals:Spring 2002 EECS150 - Lec10-cl1Page 15p0g0s0p1g1s1c1= g0+p0c0p1g2s2c2p3g3s3c3= g2+p2c2p4g4s4p5g5s5p6g6s6c6p7g7s7c0c5= g4+p4c4c7= g6+p6c6c4c2=G8+P8c0P8=p0p1G8=g1+p1g0P9=p2p3c6=Ga+Pac4Pa=p4p5Ga=g5+p5g4Pb=p6p7G9=g3+p3g2Gb=g7+p7g6c4=Gc+Pcc0Pc=P8P9Gc=G9+P9G8Pd=PaPbGd=Gb+PbGac8=Ge+Pec0Pe=PcPdGe=Gd+PdGcc0c4c88-bit Carry Look-ahead Adder with 2-input gates.Spring 2002 EECS150 - Lec10-cl1Page 16Adders in


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Berkeley COMPSCI 150 - Lecture 10 - Combinational Logic Circuits Part 1

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