University of California at BerkeleyCollege of EngineeringDepartment of Electrical Engineering and Computer ScienceEECS 150 Spring 2000Lab 2Finite State Machine1 ObjectivesYou will enter and debug a Finite State Machine (FSM). Using a definition of the problem and ourlogic equations specifying the FSM’s operation, you will enter your design in the schematic editor andsimulate it with the logic simulator.2 Prelaba) Complete your IN1 (INput 1) and IN2 (INput 2) blocksb) Write a .cmd (command) file to test your CLB (Combinational Logic Block).c) Write one single .cmd file with all the FSM test scenarios specified in the check-off sheet.d) Do as much as possible before your scheduled lab time. There is much to do in this lab. Some canbe done on paper; the remainder can be done on the computers outside of lab time.3 High-level SpecificationYou are building the controller for a 2-bit serial lock used to control entry to a locked room. Thelock has a RESET button, an ENTER button, and two two-position switches, CODE1 and CODE0, forentering the combination. For example, if the combination is 01-11, someone opening the lock would firstset the two switches to 01 (CODE1 = low, CODE0 = high) and press ENTER. Then s/he would set thetwo switches to 11 (CODE1 = high, CODE0 = high) and press ENTER. This would cause the circuit toassert the OPEN signal, causing an electromechanical relay to be released and allowing the door to open.Our lock is insecure with only sixteen different combinations; think about how it might be extended.If the person trying to open the lock makes a mistake entering the switch combination, s/he canrestart the process by pressing RESET. If s/he enters a wrong sequence, the circuitry would assert theERROR signal (after the second code is entered), illuminating an error light. S/he must press RESET tostart the process over.In this lab, you will enter a design for the lock’s controller in a new Xilinx project. Name this lab“lab2”. Make RESET and ENTER inputs. Simulate by pressing the ENTER button by forcing it high for aclock cycle. Use a two-bit wide input bus called CODE[1:0] for the two switches. (Information on how touse buses will be given later in this handout). The outputs are an OPEN signal and an ERROR signal.Figure 1 shows the state transition diagram for the combination lock controller, whose inputs andoutputs are described, in the following table:Input SignalDescriptionRESETClear any entered numbersENTERRead the switches (enter a number in the combination)CODE[1:0]Two binary switchesOutput SignalDescriptionOPENLOCKLock opensERRORIncorrect combinationFigure 1: State Transition Diagram.In the state transition diagram, states are labeled with names and state encodings. The outputs,OPEN and ERROR are 0 except where marked.4 Low-level specificationFigure 2 shows a block diagram for the combination lock controller.Figure 2: Block Diagram.MYCLBMYDFFIN1IN2NS[2:0]STATE[2:0]CLKOPENLOCKERRORFFRESETCOM1COM2RESETENTERCODE[1:0]START:000OK1:001 BAD1:101OK2:010BAD2:110OPENLOCK=1ERROR=1ENTER'RESETRESETRESET RESETENTER& COM1ENTER& COM1'ENTER' &RESET'ENTER& COM2RESET'ENTER' &RESET'ENTER & COM2'ENTERRESET'4.1 IN1 (INput 1) and IN2 (INput 2)Blocks IN1 and IN2 process the input signals COM1 (COMpare 1) and COM2 (COMpare 2) intoa simpler form for the FSM. Specifically, COM1 is asserted when CODE[1:0] is the combination’s firstnumber. Similarly, COM2 is asserted for the second number. Partitioning the circuit in this way makes thecombination easy to change.Choose your own combination; the two numbers must be different.This should be a simple block. Use a few AND gates and inverters.4.2 MYCLBThe MYCLB (MY Combinational Logic Block) block takes RESET, ENTER, COM1, COM2, andpresent state and generates OPENLOCK and ERROR, as well as the next state.The truth-table resulting from the state transition diagram is shown in table 1. We have optimizedthe logic equations for you. The equations are shown in figure 3. The variables beginning with “T” areintermediates – made up to simplify the equations.Table 1: Truth-table for MYCLB.RESET ENTER COM1 COM2 S[2:0] NS[2:0] ENTEROPENLOCK1 X X X XXX 000 0 00 0 X X 000 000 0 00 1 0 X 000 101 0 00 1 1 X 000 001 0 00 0 X X 001 001 0 00 1 X 0 001 110 0 00 1 X 1 001 010 0 00 X X X 010 010 0 10 0 X X 101 101 0 00 1 X X 101 110 0 00 X X X 110 110 1 0T0=RESET’ S1 S0’T1=RESET’ S1’T2=ENTER S2’ S0’T3=ENTER’ S0 + T2T4=COM2’ ENTER + S2T5=COM1’ T6 + T4 S0T6=ENTER S0’ERROR=S2 T0OPENLOCK=S2’ T0NS[0]=T1 T3NS[1]=T0 + ENTER T1 S0NS[2]=ERROR + T1 T5Figure 3: Logic Equations for MYCLB.Create a schematic and symbol for MYCLB, implementing the equations of Figure 3. You mayfind it helpful to study the various flavors of the AND, OR, and SOP (sum-of-products) librarycomponents. Some flavors have inverted inputs, making them perfect for equations with primed literals.4.3 MYDFF(MY D Flip-Flops)Create a block called MYDFF that contains three D flip-flops (one for each state bit) with anasynchronous clear hooked to a pin called FFRESET (Flip-Flop RESET). The flip-flops you should useare the FDC (D Flip-flop with asynchronous Clear) flip-flops. Externally, connect FFRESET to 0 (i.e., notresetting), but during simulation you can force this to 1 to reset every flip-flop.5 BusesBuses are supported by the Xilinx software. Buses are collections of wires drawn as one byclicking on the “Draw Buses” icon and drawing as if you were drawing a wire.As with wires, to end a bus you click on the right mouse button and select a method to end the bus.You have a choice of “Add Bus Terminal”, “Add Bus Label”, or “Add Bus End”.“Add Bus Terminal” is how you want to end buses that will be connected to a symbol’s pins(inputs and outputs) when drawing a symbol’s schematic (reviewing how input and output wires weredrawn in symbols in lab 1 may help make this easier to understand). Remember to specify whether theterminal is an input or output terminal. Also you will be required to input a name and how many wires thebus is made up of. It doesn’t matter whether you set the range from, say, for an eight-bit bus, 7 to 0, or from0 to 7, but it is necessary to be consistent in your all of your labeling. In labs where you’re using a TAschematic, it will usually be necessary to use 7 to 0. For this lab we will not use complex buses but theymay be useful to you when doing later labs and when doing the project. Complex buses allow
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