Chapter # 4: Programmable and Steering Logic Contemporary Logic Design Randy H. Katz University of California, Berkeley June 1993Chapter OverviewPALs and PLAsSlide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Non-Gate LogicSteering Logic: SwitchesSteering LogicSlide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Multiplexers/SelectorsSlide 32Slide 33Slide 34Multiplexer/SelectorSlide 36Slide 37Decoders/DemultiplexersSlide 39Slide 40Slide 41Decoder/DemultiplexerSlide 43Multiplexers/DecodersSlide 45Tri-State and Open-CollectorTri-state and Open CollectorSlide 48Tri-State and Open CollectorSlide 50Slide 51Read-Only MemoriesSlide 53Slide 54Slide 55Combinational Logic Word ProblemsSlide 57Slide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68Slide 69Slide 70Slide 71Slide 72Slide 73Slide 74Chapter ReviewContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-1Chapter # 4: Programmable andSteering LogicContemporary Logic DesignRandy H. KatzUniversity of California, BerkeleyJune 1993Contemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-2Chapter Overview• PALs and PLAs• Non-Gate Logic Switch Logic Multiplexers/Selecters and Decoders Tri-State Gates/Open Collector Gates ROM• Combinational Logic Design Problems Seven Segment Display Decoder Process Line Controller Logical Function Unit Barrel ShifterContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-3PALs and PLAsPre-fabricated building block of many AND/OR gates (or NOR, NAND)"Personalized" by making or breaking connections among the gatesProgrammable Array Block Diagram for Sum of Products FormInputs Dense array of AND gates Product terms Dense array of OR gates OutputsContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-4PALs and PLAsExample:F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + AEquationsPersonality MatrixKey to Success: Shared Product Terms1 = asserted in term0 = negated in term- = does not participate1 = term connected to output0 = no connection to outputInput Side:Output Side:Outputs Inputs Product t erm Reuse of t erms A 1 - 1 - 1 B 1 0 - 0 - C - 1 0 0 - F 0 0 0 0 1 1 F 1 1 0 1 0 0 F 2 1 0 0 1 0 F 3 0 1 0 0 1 A B B C A C B C AContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-5PALs and PLAsExample ContinuedAll possible connections are availablebefore programmingContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-6PALs and PLAsExample ContinuedUnwanted connections are "blown"Note: some array structureswork by making connectionsrather than breaking themContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-7PALs and PLAsAlternative representation for high fan-in structuresShort-hand notationso we don't have todraw all the wires!Notation for implementingF0 = A B + A' B'F1 = C D' + C' DContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-8PALs and PLAsABCABCABCABCABCABCABCABCABCABCF1 F2 F3 F4 F5 F6Design ExampleF1 = A B CF2 = A + B + CF3 = A B CF4 = A + B + CF5 = A xor B xor CF6 = A xnor B xnor CMultiple functions of A, B, CContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-9PALs and PLAsWhat is difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA)?PAL concept — implemented by Monolithic Memories constrained topology of the OR ArrayA given column of the OR arrayhas access to only a subset ofthe possible product termsPLA concept — generalized topologies in AND and OR planesContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-10PALs and PLAsDesign Example: BCD to Gray Code ConverterTruth TableK-mapsW = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'Minimized Functions:A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X X X X X X X 0 0 0 0 1 1 0 0 0 0 X X X X X X Y 0 0 1 1 1 1 1 1 0 0 X X X X X X Z 0 1 1 0 0 0 0 1 1 0 X X X X X X AB CD 00 01 11 10 00 01 11 10 D B C A 0 0 X 1 0 1 X 1 0 1 X X 0 1 X X K-map for W AB CD 00 01 11 10 00 01 11 10 D B C A 0 1 X 0 0 1 X 0 0 0 X X 0 0 X X K-map for X AB CD 00 01 11 10 00 01 11 10 D B C A 0 1 X 0 0 1 X 0 1 1 X X 1 1 X X K-map for Y AB CD 00 01 11 10 00 01 11 10 D B C A 0 0 X 1 1 0 X 0 0 1 X X 1 0 X X K-map for ZContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-11PALs and PLAsProgrammed PAL:4 product terms per each OR gateA B C D000000Contemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-12PALs and PLAsCode Converter Discrete Gate Implementation4 SSI Packages vs. 1 PLA/PAL Package!B \ B C C A D \ D D W X Y B B B B C C A D \ A \ C \ B \B \C \A \ D 2 2 1 1: 7404 hex inverters 2,5: 7400 quad 2-input NAND 3: 7410 t ri 3-input NAND 4: 7420 dual 4-input NAND 4 4 3 3 5 Z 1 3 2 1 2 D 1 1 4 2Contemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-13PALs and PLAsAnother Example: Magnitude ComparatorEQ NE LT GTABCDABCDABCDABCDACACBDBDABDBCDABCBCDAB CD 00 01 11 10 00 01 11 10 D B C A 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 K-map for EQ AB CD 00 01 11 10 00 01 11 10 D B C A 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 K-map for NE AB CD 00 01 11 10 00 01 11 10 D B C A 0 0 0 0 1 0 0 0 1 1 0 1 1 1 0 0 K-map for L T AB CD 00 01 11 10 00 01 11 10 D B C A 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 0 K-map for GTContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-14Non-Gate LogicAND-OR-InvertPAL/PLAGeneralized Building BlocksBeyond Simple GatesIntroductionKinds of "Non-gate logic": • switching circuits built from CMOS transmission gates • multiplexer/selecter functions • decoders • tri-state and open collector gates • read-only memoriesContemporary Logic DesignProg. & Steering Logic© R.H. Katz Transparency No. 4-15Steering Logic: SwitchesVoltage Controlled SwitchesGateOxideSource DrainSilicon BulkChannel RegionMetal Gate, Oxide, Silicon SandwichDiffusion regions: negatively charged ions driven into Si surfaceSi Bulk: positively charged ionsBy "pulling" electrons to the surface, a
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