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Berkeley COMPSCI 150 - Debugging

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DebuggingToday (1)Today (2)Simulation vs. Hardware (1)Simulation vs. Hardware (2)Simulation vs. Hardware (3)Debugging (1)Debugging (2)Debugging (3)Debugging (4)Debugging (5)Debugging (6)Debugging (7)Administrative InfoLab #4 - DebuggingPart1: Bottom Up Testing (1)Part1: Bottom Up Testing (2)Part1: Bottom Up Testing (3)Part1: Bottom Up Testing (4)Part1: Bottom Up Testing (5)Part1: Bottom Up Testing (6)Part1: Bottom Up Testing (7)Part1: Bottom Up Testing (8)Part2: Test Hardware (1)Part2: Test Hardware (2)Part2: Test Hardware (3)Part3: FSM Testing (1)Part3: FSM Testing (2)01/14/19 EECS150 Lab Lecture #4 1DebuggingEECS150 Fall 2007 – Lab Lecture #4Shah Bawany2/9/2007 EECS150 Lab Lecture #4 2Today (1)Simulation vs. HardwareDebuggingAlgorithmGoalsTipsAdministrative Info2/9/2007 EECS150 Lab Lecture #4 3Today (2)Lab #4Bottom Up Testing (Peak Detector)Designing Test Hardware (Broken Adder)Exhaustive FSM Testing (Broken FSM)2/9/2007 EECS150 Lab Lecture #4 4Simulation vs. Hardware (1)Debugging in SimulationSlow Running TimeFast DebuggingWaveformsText messagesFull VisibilityCan examine any signalEasy to FixA few minutes to compile and resimulateModelsim assumes no gate delay2/9/2007 EECS150 Lab Lecture #4 5Simulation vs. Hardware (2)Debugging in HardwareFast Running TimeFull speed in factSlow DebuggingSynthesis can take hoursLittle or No VisibilityVery hard to probe signals2/9/2007 EECS150 Lab Lecture #4 6Simulation vs. Hardware (3)SimulationFunctional Testing & VerificationTest everything at least minimallyFully Verify what you canThis will save you many sleepless nightsHardwareDebuggingTreat this as a last resortIt is painfulHowever, it will sometimes be necessary (wireless)2/9/2007 EECS150 Lab Lecture #4 7Debugging (1)Debugging AlgorithmHypothesis: What’s broken?Control: Give it controlled test inputsExpected Output: What SHOULD it do?Observe: Did it work right?If it broke: THAT’S GREAT!If we can’t break anything like this then the project must be working…2/9/2007 EECS150 Lab Lecture #4 8Debugging (2)Don’t debug randomlyJust changing things at random often makes things look fixedIt won’t really helpDebug systematicallyYour first design may be the bestWhat can you do?2/9/2007 EECS150 Lab Lecture #4 9Debugging (3)High Level DebuggingLocalize the problemSDRAM? Video?Test PatternsLets you easily isolate the broken componentIf you know exactly what’s going in you can check what’s coming out2/9/2007 EECS150 Lab Lecture #4 10Debugging (4)Simulate the broken component(s)Writing test benches takes less time than sitting around wondering why its brokenEveryone hates writing testbenches(Even me)Get used to it2/9/2007 EECS150 Lab Lecture #4 11Debugging (5)Your best debugging tool is logicIf 3 out of 4 components work, what’s broken?Question all your assumptions!Just because you think its true doesn’t mean it is90% of debugging time is wasted debugging the wrong problem otherwiseGiven solutions and modules may not work the way you expect!2/9/2007 EECS150 Lab Lecture #4 12Debugging (6)Before you change anythingUnderstand exactly what the problem isFind an efficient solutionEvaluate alternative solutionsAfter the changeFixes may make things worse sometimesMay uncover a second bugMay be an incorrect fixRepeat the debugging process2/9/2007 EECS150 Lab Lecture #4 13Debugging (7)Ask aroundSomeone else may have had the same bugThey’ll probably at least know about where the problem isDifferent bugs may produce the same resultsTAsThe TAs know common problemsWe’re here to help, not solve it for you2/9/2007 EECS150 Lab Lecture #4 14Administrative InfoMidterm IThursday 9/27Reviews session is:Tuesday 9/25, 8-10pm, 125 CoryPartnersYou MUST have one for this weekRestrictionsYou can change partners until the project startsYou must be checked off in the same labProject begins in 2 weeks!2/9/2007 EECS150 Lab Lecture #4 15Lab #4 - DebuggingPart 1: Bottom Up TestingPart 2: Hardware TestingPart 3: FSM Testing2/9/2007 EECS150 Lab Lecture #4 16Part1: Bottom Up Testing (1)What if EqualOut = 1’b0 and GreaterOut = 1’b0?Lab4Comp12/9/2007 EECS150 Lab Lecture #4 17Part1: Bottom Up Testing (2)Exhaustive TestingIdeal Testing MethodCircuit is 100% tested!Requires us to test a LOT!Can we do it here? (24 possible inputs)MethodMake a truth tableHave the testbench generate all inputsMake sure outputs match truth table2/9/2007 EECS150 Lab Lecture #4 18Part1: Bottom Up Testing (3)Lab4Comp1 Lab4Comp1 Lab4Comp1 Lab4Comp1Lab4Comp42/9/2007 EECS150 Lab Lecture #4 19Part1: Bottom Up Testing (4)Exhaustive Testing?28 = 256 Possible InputsMethodUse a for loop to generate all inputsLoops allowed only in testbenchesThey will not synthesizeCompare against a “>=“Print a message if they differ2/9/2007 EECS150 Lab Lecture #4 20Part1: Bottom Up Testing (5)Lab4PeakDetector2/9/2007 EECS150 Lab Lecture #4 21Part1: Bottom Up Testing (6)Exhaustive Testing?24 = 16 Possible Inputs24 = 16 Possible States16*16 = 256 combinationsWe could do it in this caseCan’t exhaustively test most FSMsToo many state/input combinationsMust rely on directed testing2/9/2007 EECS150 Lab Lecture #4 22initial beginendPart1: Bottom Up Testing (7)integer i;reg [3:0] TestValues[1:16];$readmemh("TestValues.txt", TestValues);for(i = 1; i <= 16; i = i + 1) begin#(`Cycle);In = TestValues[i]; $display("In = %d, Peak = %d", In, Peak);end2/9/2007 EECS150 Lab Lecture #4 23Part1: Bottom Up Testing (8)Read Test Vectors from a FileDesigning Test VectorsMake sure to cover most casesWe want 95%+ coverageDesigning test vectors is a “black art”“$” ProcessesNot synthesizeableMore information in IEEE Verilog Reference2/9/2007 EECS150 Lab Lecture #4 24Part2: Test Hardware (1)Lab4 Part2Lab4Part2TesterFailModeFailMode2/9/2007 EECS150 Lab Lecture #4 25Part2: Test Hardware (2)Test ProcedureHit Reset (SW1)Hit Go (SW2)Record an errorDD1-8 show {A, B}SW10[1] selects the sum on DD4-8Hit GoRepeat until the tester stops2/9/2007 EECS150 Lab Lecture #4 26Part2: Test Hardware (3)The Broken Adder16bit Adder232 ≈4 Billion Test VectorsCan’t simulate this


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Berkeley COMPSCI 150 - Debugging

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