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Berkeley COMPSCI 150 - Checkpoint 1 SDRAM

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EECS150 Spring 2008 Checkpoint 1UCB 1 2008UNIVERSITY OF CALIFORNIA AT BERKELEYCOLLEGE OF ENGINEERINGDEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCECheckpoint 1SDRAMIntroductionWelcome to Checkpoint #1. Read this document thoroughly and get started early. Thischeckpoint is meant to ease your transition into this semester’s project; however, it wouldbe a mistake to take it lightly. Initial Advice: When we tell you that you need to readthe Datasheets – READ THEM!1.0 MotivationThis checkpoint serves three purposes:1. Familiarize you with working with SDRAM2. Build a simple SDRAM interface for later use in the project3. Give you practice on reading specification sheetsIt is important to be familiar with SDRAM as it is an increasingly commoncomponent in many designs. In addition to providing large, cheap storage for projectslike those in EECS150, SDRAM forms the heart of every computer.Most digital designs are only as useful as the amount of storage they contain.Even streaming Digital Signal Processing (DSP) applications, the canonical example of astateless or memory-less design often require significant amounts of RAM forcomputations like matrix transposes, FFT and delays.Because it is so expensive to build large or fast SRAM, DRAM has becomenearly ubiquitous. The largest hurdle to using DRAM is that it must be “refreshed”periodically in order to maintain its contents. The second largest problem with any kindof RAM is often that it is asynchronous, making it difficult to interface with. Both ofthese are somewhat mitigated by using Synchronous DRAM or SDRAM, which providesa synchronous interface with guaranteed timing, including a 3 cycle command sequencewhich will automatically perform a refresh operation.Because of its relative ease of use, and nearly universal inclusion in large digitaldesigns, SDRAM is likely to remain a permanent part of digital design for many years tocome. Therefore this checkpoint is meant not only to provide you an easy way to bufferdata, which will simplify your project, but will also give you significant experience inworking with SDRAM.At this point in class, you are expected to be able to design and implement a largemajority of the circuits on your own. This documentation is meant only as a loose guide,and you should feel free to alter any specifications you feel necessary. Figures andnumbers presented here should only be used conceptually. Actual timing charts providedby Xilinx should be used when designing your circuit.EECS150 Spring 2008 Checkpoint 1UCB 2 2008“BECAUSE YOU WILL BE KEEPING AND RELYING ON THIS CODE FOR MONTHS, ITWILL ACTUALLY SAVE YOU MANY STRESSFUL HOURS TO ENSURE IT WORKS WELL NOW,RATHER THAN WHEN YOU ARE ABOUT TO FINISH THE PROJECT”2.0 OverviewFigure 1 below shows the basic datapath you will be implementing forCheckpoint # 1. You will build the SDRAM subsystem that will read and write valueswe supply into the SDRAM module. The black box provided will calculate whether ornot you are storing and retrieving data properly – it will display a count of the times thatyour data is wrong on the LEDs.This will be the first piece of the project. You should read the data sheets andfully understand the operation of the 3rd party devices you will be interfacing withbefore you come to your lab section.In addition, you will be required to present your design at an initial design reviewwith your TA at the start of this week’s lab. Do not skimp or rush through your design,doing so will cost you many hours of frustration later this week!!Figure 1: Checkpoint 1 DatapathEECS150 Spring 2008 Checkpoint 1UCB 3 20082.1 SDRAM SubsystemThe modules you will building for this checkpoint are a combination of a protocolbridge and a command FSM, which will take care of issuing and timing SDRAMcommands, leaving your other modules free to ignore the details of working withSDRAM.The primary responsibilities of your SDRAM Control module are:1. Initialize SDRAMa. Wait at least 100us after resetb. Issue an initialization sequence to properly set-up the SDRAM(See pages 12-14 and 40 of the SDRAM Datasheet)2. Issue SDRAM commandsa. When a read or a write is ready, it should be sent to the SDRAMb. Your module must take care to ensure proper burst timing (Seepages 46, 51, 53, 58 of the SDRAM Datasheet)Essentially your SDRAM Control module will abstract away the fact that you areworking with SDRAM, both by taking care of the detailed and specific timingrequirements.3.0 PrelabPlease make sure to complete the prelab before you attend your lab section. Youwill not be able to finish this checkpoint in 3hrs! Labs are getting progressivelylonger.1. Read this handout thoroughly.a. Pay particular attention to section 4.0 Lab Procedure as itdescribes what you will be doing in detail.2. Examine the documents page of the websitea. You will need to get used to reading datasheets, like these.They form the core of information available to hardwaredesigners.b. http://www-inst.eecs.berkeley.edu/~cs150/fa04/Documents.htm#Datasheetsc. Read the MT48LC16M16 Datasheetd. It is expected that you use the data sheets as your primarysource of information.3. Examine the Verilog provided for this checkpointa. There isn’t much, so it should be pretty clearb. FPGATop will be provided.4. Start your design ahead of time.a. Begin with schematics and bubble-and-arc diagrams i. Make sure to design your SDRAM Controller FSMcarefully.b. Come prepared for your design reviewEECS150 Spring 2008 Checkpoint 1UCB 4 2008 i. You will need to provide bubble and arc diagrams as wellas high level design schematics.c. Start building your testbenches early i. Perhaps have one person design a module and the otherdesign a testbench, and then switch. ii. You cannot pass this checkpoint without good testbenchesd. Make sure you understand tri-state and how to implement this inverilog. i. You should bring as part of your design review the 1 line ofcode that will implement the necessary tri-state for thischeckpoint.5. This will be the longest lab that you have ever done, plan accordingly.a. You will need to test and debug your Verilog thoroughly.b. You must build a reliable interface with a real hardwarecomponent!4.0 Lab


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Berkeley COMPSCI 150 - Checkpoint 1 SDRAM

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