10-4-2007 Lec12 EECS150 Fa071EECS 150 - Components and Design Techniques for Digital SystemsLec 12 - Timing David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs15010-4-2007 Lec12 EECS150 Fa072Outline• Performance Limits of Synchronous Systems• Delay in logic gates• Delay in wires• Delay in combinational networks• Clock Skew• Delay in flip-flops• Glitches10-4-2007 Lec12 EECS150 Fa073Recall: General Model of Synchronous Circuit• All wires, except clock, may be multiple bits wide.• Registers (reg)– collections of flip-flops• clock– distributed to all flip-flops– typical rate?• Combinational Logic Blocks (CL)– no internal state– output only a function of inputs• Particular inputs/outputs are optional• Optional Feedbackreg regCL CLclock inputoutputoption feedbackinputoutput10-4-2007 Lec12 EECS150 Fa074General Model of Synchronous Circuit• How do we measure performance?– operations/sec?– cycles/sec?• What limits the clock rate?• What happens as we increase the clock rate?reg regCL CLclock inputoutputoption feedbackinputoutput10-4-2007 Lec12 EECS150 Fa075Limitations on Clock Rate1 Logic Gate Delay• What are typical delay values?2 Delays in flip-flops• Both times contribute to limiting the clock period.tinputoutputDclkQsetup time clock to Q delay• What must happen in one clock cycle for correct operation?• Assuming perfect clock distribution (all flip-flops see the clock at the same time):– All signals must be ready and “setup” before rising edge of clock.10-4-2007 Lec12 EECS150 Fa076Example: Parallel-Serial ConverterabT ≥ time(clk→Q) + time(mux) + time(setup)T ≥τclk→Q+ τmux+ τsetupclk10-4-2007 Lec12 EECS150 Fa077General Model of Synchronous Circuit• In general, for correct operation:for all paths.• How do we enumerate all paths?– Any circuit input or register output to any register input or circuit output.– “setup time” for circuit outputs depends on what it connects to– “clk-Q time” for circuit inputs depends on from where it comes.reg regCL CLclock inputoutputoption feedbackinputoutputT ≥ time(clk→Q) + time(CL) + time(setup)T ≥τclk→Q+ τCL+ τsetup10-4-2007 Lec12 EECS150 Fa078Recall L2: Transistor-level Logic Circuits• Inverter (NOT gate):VddGndVddGnd0 voltsin out3 voltswhat is the relationship between in and out?10-4-2007 Lec12 EECS150 Fa079Qualitative Analysis of Logic Delay• Improved Transistor Model: • We refer to transistor "strength" as the amount of current that flows for a given Vds and Vgs. • The strength is linearly proportional to the ratio of W/L– Physical property• Turn it on harder allows more current to flowpFETnFETWhat is the effective resistance?10-4-2007 Lec12 EECS150 Fa0710Gate Switching Behavior• Inverter:• NAND gate:gsdsWhen does it start? How quickly does it switch?10-4-2007 Lec12 EECS150 Fa0711Clarify your understandingWhat is the 0 Æ 1 and 1 Æ 0 behavior of a NOR gate?Why do we need pMOS and nMOS devices in a pass gate?- used for tristate10-4-2007 Lec12 EECS150 Fa0712Delays in a series of gates• Cascaded gates:VoutVin10-4-2007 Lec12 EECS150 Fa0713Gate Delay due to fan out• Fan-out:• The delay of a gate is proportional to its output capacitance. Because, gates #2 and 3 turn on/off at a later time. (It takes longer for the output of gate #1 to reach the switching threshold of gates #2 and 3 as we add more output capacitance.)13210-4-2007 Lec12 EECS150 Fa0714Gate Delay with a general circuit• “Fan-in”– Does it affect the delay of the individual gate?– When does the gate begin its transition?• What is the delay in this circuit?• Critical Path: the path with the maximum delay, from any input to any output.– In general, we include register set-up and clk-to-Q times in critical path calculation.• Why do we care about the critical path?10-4-2007 Lec12 EECS150 Fa0715What is the delay through arbitrary combinational logic?10-4-2007 Lec12 EECS150 Fa0716Announcements• Reading: K&B 3.5 6.1.5-6.2.3 (were in 9/20 assignment)• K&B 10.6 is great protocol example– We’ll do several of those as we go• HW 5 out today (due 10/12)• Class survey• Lab partners10-4-2007 Lec12 EECS150 Fa0717Delay in Flip-flops• Setup time results from delay through first latch.• Clock to Q delay results from delay through secondlatch.DclkQsetup time clock to Q delayclkclk’clkclkclk’clk’clkclk’10-4-2007 Lec12 EECS150 Fa0718Wire Delay• In general, wire behave as “transmission lines”:– signal wave-front moves close to the speed of light» ~1ft/ns– Time from source to destination is called the “transit time”.– In ICs most wires are short, and the transit times are relatively short compared to the clock period and can be ignored.– Not so on PC boards.– ...Or long wires on fast chips» Busses» Global Control signals» Clock• Rule of thumb: wire must be treated as a transmission line if its length exceed λ/100.tx10-4-2007 Lec12 EECS150 Fa0719Architectural Level DelaydatapathControllerData bussesclock10-4-2007 Lec12 EECS150 Fa0720Wire Delay• Even in those cases where the transmission line effect is negligible:– Wires posses distributed resistance and capacitance– Time constant associated with distributed RC is proportional to the square of the wire length• For short wires on ICs, resistance is insignificant (relative to effective R of transistors), but C is important.– Typically around half of C of gate load is in the wires.• For long wires on ICs:– busses, clock lines, global control signal, etc.– Resistance is significant, therefore distributed RC effect dominates.– signals are typically “rebuffered” to reduce delay:v1v4v3v2timev1 v2 v3 v410-4-2007 Lec12 EECS150 Fa0721Modern rule of thumb• Transistors are cheap– And their local wires• Wire is what counts• Often pays to do extra local computation (gates) to reduce wire delay10-4-2007 Lec12 EECS150 Fa0722Clock Skew• Unequal delay in distribution of the clock signal to various parts of a circuit:– if not accounted for, can lead to erroneous behavior. (see next)– Comes about because:» clock wires have delay,» circuit is designed with a different number of clock buffers from the clock source to the various clock loads, or» buffers have unequal delay.– All synchronous circuits experience some clock skew:» more of an issue
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