Spring 2009EECS150 - Lec7-CAD2Page EECS150 - Digital DesignLecture 4 - Computer Aided Design (CAD) - Part II (Logic Simulation)Feb 10, 2009John Wawrzynek1Spring 2009EECS150 - Lec7-CAD2Page Finite State Machine Review2State Transition DiagramImplementation Circuit DiagramHolds a symbol to keep track of which bubble the FSM is in.CL functions to determine output value and next state based on input and current state.out = f(in, current state)next state = f(in, current state)What does this one do?Every Synchronous Digital System is a FSM.Spring 2009EECS150 - Lec7-CAD2Page Finite State Machinesmodule FSM1(clk, rst, in, out);input clk, rst;input in;output out;// Defined state encoding:parameter IDLE = 2'b00;parameter S0 = 2'b01;parameter S1 = 2'b10;reg out;reg [1:0] state, next_state;// always block for state registeralways @(posedge clk) if (rst) state <= IDLE; else state <= next_state;3 Must use reset to force to initial state.reset not always shown in STDout not a register, but assigned in always blockTHE register to hold the “state” of the FSM.Combinational logic signals for transition.Constants local to this module.A separate always block should be used for combination logic part of FSM. Next state and output generation. (Always blocks in a design work in parallel.)Spring 2009EECS150 - Lec7-CAD2Page FSM CL block rewritten4always @(state or in) case (state) IDLE : begin out = 1’b0; if (in == 1’b1) next_state = S0; else next_state = IDLE; end S0 : begin out = 1’b0; if (in == 1’b1) next_state = S1; else next_state = IDLE; end S1 : begin out = 1’b1; if (in == 1’b1) next_state = S1; else next_state = IDLE; end default: begin next_state = IDLE; out = 1’b0; end endcaseendmodulealways @* begin next_state = IDLE; out = 1’b0; case (state) IDLE : if (in == 1’b1) next_state = S0; S0 : if (in == 1’b1) next_state = S1; S1 : begin out = 1’b1; if (in == 1’b1) next_state = S1; end default: ; endcase endendmodule * for sensitivity listNormal values: used unless specified below.Within case only need to specify exceptions to the normal values. Note: The use of “blocking assignments” allow signal values to be “rewritten”, simplifying the specification.Spring 2009EECS150 - Lec7-CAD2Page Procedural AssignmentsThe sequential semantics of the blocking assignment allows variables to be multiply assigned within a single always block. Unexpected behavior can result from mixing these assignments in a single block. Standard rules:i. Use blocking assignments to model combinational logic within an always block ( “=”).ii. Use non-blocking assignments to implement sequential logic (“<=”).iii. Do not mix blocking and non-blocking assignments in the same always block.iv. Do not make assignments to the same variable from more than one always block.5Spring 2009EECS150 - Lec7-CAD2Page Encoder ExampleNested IF-ELSE might lead to “priority logic”Example: 4-to-2 encoderalways @(x) begin : encode if (x == 4'b0001) y = 2'b00; else if (x == 4'b0010) y = 2'b01; else if (x == 4'b0100) y = 2'b10; else if (x == 4'b1000) y = 2'b11; else y = 2'bxx; end This style of cascaded logic may adversely affect the performance of the circuit.6Spring 2009EECS150 - Lec7-CAD2Page Encoder Example (cont.)To avoid “priority logic” use the case construct:always @(x) begin : encode case (x)4’b0001: y = 2'b00; 4’b0010: y = 2'b01; 4'b0100: y = 2'b10; 4'b1000: y = 2'b11; default: y = 2'bxx; endcase end 7All cases are matched in parallel.Spring 2009EECS150 - Lec7-CAD2Page Encoder Example (cont.)A similar simplification would be applied to the if-else version also.8This circuit would be simplified during synthesis to take advantage of constant values as follows and other Boolean equalities:Spring 2009EECS150 - Lec7-CAD2Page Encoder Example (cont.)If you can guarantee that only one 1 appears in the input, then simpler logic can be generated:always @(x) begin : encode if (x[0]) y = 2'b00; else if (x[1]) y = 2'b01; else if (x[2]) y = 2'b10; else if (x[3]) y = 2'b11; else y = 2'bxx; end 9If the input applied has more than one 1, then this version functions as a “priority encoder”. The least significant 1 gets priority (the more significant 1’s are ignored). Again the circuit will be simplified when possible.Spring 2009EECS150 - Lec7-CAD2Page Verilog in EECS150• Primarily use behavior modeling. With instantiation to build hierarchy and map to FPGA resources not supported by synthesis.• Primary Style Guidelines:– Favor continuous assign and avoid always blocks unless:• no other alternative: ex: state elements, case• they help readability and clarity of code: ex: large nested if-else-if– Use named ports. – Separate CL logic specification from state elements.– Follow our rules for procedural assignments.• Verilog is a big language. This is only an introduction. – Our text book is a good source. Read and use chapter 4.– When needed look at online IEEE Std 1364-2001 document.– Be careful of what you read on the web! Many bad examples out there.– We will be introducing more useful constructs throughout the semester. Stay tuned!10Spring 2009EECS150 - Lec7-CAD2Page Final thoughts on Verilog ExamplesVerilog may look like C, but it describes hardware! (Except in simulation test-benches - which actually behave like programs.)Multiple physical elements with parallel activities and temporal relationships.A large part of digital design is knowing how to write Verilog that gets you the desired circuit. First understand the circuit you want, then figure out how to code it in Verilog. If you do one of these activities without the other, you will struggle. These two activities will merge at some point for
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