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Berkeley COMPSCI 150 - Hardware Description Languages

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CS 150 - Spring 2007 - Lecture #4: Verilog - 1Hardware Description Languages:Verilog! Verilog" Structural Models" (Combinational) Behavioral Models" Syntax" ExamplesCS 150 - Spring 2007 - Lecture #4: Verilog - 2Quick History of HDLs! ISP (circa 1977) - research project at CMU" Simulation, but no synthesis! Abel (circa 1983) - developed by Data-I/O" Targeted to programmable logic devices" Not good for much more than state machines! Verilog (circa 1985) - developed by Gateway (now Cadence)" Similar to Pascal and C" Delays is only interaction with simulator" Fairly efficient and easy to write" IEEE standard! VHDL (circa 1987) - DoD sponsored standard" Similar to Ada (emphasis on re-use and maintainability)" Simulation semantics visible" Very general but verbose" IEEE standardCS 150 - Spring 2007 - Lecture #4: Verilog - 3Design MethodologyHDLSpecificationStructure and Function(Behavior) of a DesignSimulationVerification: DesignBehave as Required?Functional: I/O BehaviorRegister-Level (Architectural)Logic-Level (Gates)Transistor-Level (Electrical)Timing: Waveform BehaviorSynthesisGeneration: MapSpecification toImplementationCS 150 - Spring 2007 - Lecture #4: Verilog - 4Verilog/VHDL! The “standard” languages! Very similar" Many tools provide front-ends to both" Verilog is “simpler”# Less syntax, fewer constructs" VHDL supports large, complex systems# Better support for modularization# More grungy details# “Hello world” is much bigger in VHDLCS 150 - Spring 2007 - Lecture #4: Verilog - 5Verilog! Supports structural and behavioral descriptions! Structural" Explicit structure of the circuit" How a module is composed as an interconnection of moreprimitive modules/components" E.g., each logic gate instantiated and connected to others! Behavioral" Program describes input/output behavior of circuit" Many structural implementations could have same behavior" E.g., different implementations of one Boolean functionCS 150 - Spring 2007 - Lecture #4: Verilog - 6Verilog Introduction! the module describes a component in the circuit! Two ways to describe:" Structural Verilog# List of components and how they are connected# Just like schematics, but using text# Hard to write, hard to decode# Useful if you don’t have integrated design tools" Behavioral Verilog# Describe what a component does, not how it does it# Synthesized into a circuit that has this behaviorCS 150 - Spring 2007 - Lecture #4: Verilog - 7module xor_gate (out, a, b); input a, b; output out; wire abar, bbar, t1, t2; inverter invA (abar, a); inverter invB (bbar, b); and_gate and1 (t1, a, bbar); and_gate and2 (t2, b, abar); or_gate or1 (out, t1, t2);endmoduleStructural Model" Composition of primitive gates to form more complex module" Note use of wire declaration!By default, identifiersare wiresCS 150 - Spring 2007 - Lecture #4: Verilog - 8Structural Model! Example of full-addermodule full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin;endmodulemodule adder4 (A, B, Cin, S, Cout); input [3:0] A, B; input Cin; output [3:0] S; output Cout; wire C1, C2, C3; full_addr fa0 (A[0], B[0], Cin, S[0], C1); full_addr fa1 (A[1], B[1], C1, S[1], C2); full_addr fa2 (A[2], B[2], C2, S[2], C3); full_addr fa3 (A[3], B[3], C3, S[3], Cout);endmoduleBehaviorStructuralCS 150 - Spring 2007 - Lecture #4: Verilog - 9module and_gate (out, in1, in2); input in1, in2; output out; assign out = in1 & in2;endmoduleSimple Behavioral Model! Combinational logic" Describe output as a function of inputs" Note use of assign keyword: continuous assignmentOutput port of a primitive mustbe first in the list of portsRestriction does not apply tomodulesCS 150 - Spring 2007 - Lecture #4: Verilog - 10Verilog Data Types and Values! Bits - value on a wire" 0, 1" X - don’t care/don’t know" Z - undriven, tri-state! Vectors of bits" A[3:0] - vector of 4 bits: A[3], A[2], A[1], A[0]" Treated as an unsigned integer value# e.g. , A < 0 ??" Concatenating bits/vectors into a vector# e.g., sign extend# B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]};# B[7:0] = {4{A[3]}, A[3:0]};" Style: Use a[7:0] = b[7:0] + c; Not: a = b + c; // need to look at declarationCS 150 - Spring 2007 - Lecture #4: Verilog - 11Verilog Numbers! 14 - ordinary decimal number! -14 - 2’s complement representation! 12’b0000_0100_0110 - binary number with 12 bits (_ isignored)! 12’h046 - hexadecimal number with 12 bits! Verilog values are unsigned" e.g., C[4:0] = A[3:0] + B[3:0];" if A = 0110 (6) and B = 1010(-6) C = 10000 not 00000i.e., B is zero-padded, not sign-extendedCS 150 - Spring 2007 - Lecture #4: Verilog - 12Verilog OperatorsCS 150 - Spring 2007 - Lecture #4: Verilog - 13Verilog “Variables”! wire" Variable used simply to connect components together! reg" Variable that saves a value as part of a behavioral description" Usually corresponds to a wire in the circuit" Is NOT necessarily a register in the circuit! The Rule:" Declare a variable as a reg if it is the target of a concurrent (non-blocking) assignment statement# Don’t confuse reg assignments with the combinational continuous assignstatement!# Reg should only be used with always blocks (sequential logic, to bepresented …)# Confusing isn’t it?CS 150 - Spring 2007 - Lecture #4: Verilog - 14Verilog Module! Corresponds to a circuit component" “Parameter list” is the list of external connections, aka “ports”" Ports are declared “input”, “output” or “inout”# inout ports used on tri-state buses" Port declarations imply that the variables are wiresmodule full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin;endmodulemodule nameinputs/outputsportsCS 150 - Spring 2007 - Lecture #4: Verilog - 15assign A = X | (Y & ~Z);assign B[3:0] = 4'b01XX;assign C[15:0] = 16'h00ff;assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin;use of arithmetic operatormultiple assignment (concatenation)delay of performing computation, only used by simulator, not synthesisuse of Boolean operators(~ for bit-wise, ! for logical negation)bits can take on four values(0, 1, X, Z)variables can be n-bits wide(MSB:LSB)Verilog Continuous Assignment! Assignment is continuously evaluated! assign corresponds to a connection or a simple component withthe described function! Target is NEVER a reg variableCS 150 - Spring 2007 - Lecture #4: Verilog - 16module


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