EECS 150 Spring 2007 Lab 1 UCB 1 2007 UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 1 FPGA CAD Tools ASSIGNED: Week of 1/21 DUE: Week of 1/28, 10 minutes after start of your assigned lab section. 1.0 Motivation In this lab you will take a simple design through the FPGA Computer Aided Design (CAD) tool-flow, starting from design entry all the way to programming the hardware. This lab will give you experience with the software that you’ll be using for the rest of the semester. 2.0 Introduction to the CAD Flow Figure 1 below shows the general CAD tool flow to which you have access in this lab. Highlighted in bold is the flow which we will be using. A design written in Verilog using Notepad is fed through Synplify Pro, the Xilinx PAR tools and finally iMPACT which will program it into the FPGA. The whole process is described in detail below. Figure 1: General CAD Tool Flow 2.1 Design Entry The first step in logic design is to conceptualize your design. Once you have a good idea about the function and structure of your circuit and maybe a few block diagram sketches, you can start the implementation process by specifying your circuit in a more formal manner.EECS 150 Spring 2007 Lab 1 UCB 2 2007 In this class we will use a Hardware Description Language (HDL) called Verilog. HDLs have several advantages over other methods of circuit specification: 1. Ease of editing, since files can be written using any text editor 2. Ease of management when dealing with large designs 3. The ability to use a high-level behavioral description of a circuit. In this class we will default to using Notepad to edit Verilog. Fancier editors are available, and in fact are included with the CAD tools such as Project Navigator and ModelSim; however these tools are slow and will often hinder you. For this lab, we will provide you with a complete and working project in Verilog. 2.2 Simulation With a design in hand, the first step is always to test it using an HDL simulator. Because actually implementing any large design can take upwards of half an hour, it is much too time consuming to simply synthesize a design, check to see if it works and then tweak it. In fact, because a fully implemented design in hardware runs so quickly (at megahertz clock frequencies) and involves so many signals, even if implementation took a mere 30 sec, it is highly impractical to debug the final hardware implementation directly. To speed up the design cycle and also to provide the designer, you, with more detailed information about the functioning of a running circuit, we use HDL simulators such as ModelSim. Simulation allows you to provide specific test inputs to your circuit and observe both the outputs and the internal operation of your circuit giving you very detailed feedback as to what is happening and when. Because simulation is software rather than hardware-based, it is relatively slow taking perhaps 5 min to simulate 5 msec of real time. But it allows you to create very specific input conditions, using special Verilog modules called “testbenches” to exercise your circuit. You can even to print out text messages in the event of problems, rather than forcing you to look at the binary output of your circuit. 2.3 Synthesis Once a design is entered, simulated and debugged, the next step in the CAD Tool Flow is synthesis. It is the job of the synthesis program to translate the Verilog description of the circuit into an equivalent circuit made of primitive circuit components that can be directly implemented in an FPGA. In a way, the synthesis tool is almost like a compiler. Where a compiler translates a high level language, such as C, into a sequence of primitive commands that can be directly executed on a processor, synthesis translates a high level language, in this case Verilog, into primitive circuit components that can be directly implemented on an FPGA. The final product of a synthesis tool is a netlist file, a text file that contains a list of all the instances of primitive components in the translated circuit and a description of how they are connected. 2.4 Place and Route From the netlist produced by the synthesis tool, we must somehow create a file containing the bits needed to configure the LUTs, Switchboxes, Flip-Flops, and other resources that make up the FPGA. This is the job of the Place and Route (PAR) tools.EECS 150 Spring 2007 Lab 1 UCB 3 2007 2.4.1 Placement To properly connect the various FPGA resources our design will use, the tools must first take each LUT, Flip-Flop or other resource called for in the netlist and decide which physical piece of the FPGA will play that role. For example, a 4LUT implementing the function of a 4-input NAND gate in a netlist could be placed in any of the 38,400 4LUTs in a Xilinx Virtex XCV2000E FPGA chip. Clever choice of placement will make the subsequent routing easier and result a circuit with less delay. 2.4.2 Routing Once the components are placed, the proper connections must be made. This step is called routing, because the tools must choose, for each signal, one of the millions of paths to get that signal from its source to its destination. Because the number of possible paths for a given signal is very large, and there are many signals, this is typically the most time consuming part of implementing a design, aside from specification. Planning your design well and making it compact and efficient will significantly reduce how long this step takes. Designing your circuit well can cut the time it takes to route from 30 min to 30 sec. 2.4.3 Place and Route Tools Unlike synthesis, which need only know a set of primitive components to express its result, placement and routing are dependent upon the specific size and structure of the target FPGA. Because of this the FPGA vendor, Xilinx in our case, usually provides the placement and routing programs, whereas a third party, Synplicity, can often provide more powerful and more general synthesis tools. The end product after placement and routing is a *.bit file containing the stream of bits used to configure the FPGA. Note: placement and routing are NP hard optimization problems and the
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