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Berkeley COMPSCI 150 - Testing Methodologies

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Testing MethodologiesDesign ProcessSlide 3TestingWhy Manufacture Test?Slide 6Testing of Logic CircuitsFault ModelSlide 9Slide 10Problems with Fault ModelPath SensitizationSlide 13Slide 14Fault PropagationSlide 16Tree Structured CircuitsSlide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Random TestingAnnouncementsSequential TestingScan Path TechniqueScan Path ExampleSlide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Built-in Self-Test (BIST)Many Types of BIST Engines-ExamplesLinear Feedback Shift RegisterSlide 44Slide 45Complete Self-Test SystemPutting it all TogetherCurrent Status on Manufacture TestBring-UpSummaryCS 150 - Fall 2007 – Lec. #23: Testing - 1Testing MethodologiesSarah Bird*Many Slides from Randy Katz from Spring 2007 and Kurt Keuzter from Fall 2007CS 150 - Fall 2007 – Lec. #23: Testing - 2Start with Some SpecificationThis Class: Lab Write UpsIndustry: Contract Restrictions High and Low-Level Specifications from Architects and DesignersConvert the Design to HDLThis Class: You design MicroarchitectureWrite Verilog using components provided by the TA’s or the Standard Library and also from scratchIndustry: Verilog or VHDL using standard components or previous designsSpecificationDesign ProcessNetlistHDLNetlistLayoutFinal ProductManual Design and CodingRTL SynthesisLogic OptimizationPhysical DesignImplemetationCS 150 - Fall 2007 – Lec. #23: Testing - 3Convert HDL into RTL and Optimize DesignThis Class: Synplify ProIndustry: Other Synthesis tools2 & Multi-Level Logic OptimizationConvert the Netlist into a LayoutThis Class: Xilinx Map & PAR Industry: Place and Route ToolsTechnology MappingConvert Layout to Final ProductThis Class: Download to Board..Configure FPGA Industry: Send Layout to FabMake MasksManufacture ChipsSpecificationDesign ProcessNetlistHDLNetlistLayoutFinal ProductManual Design and CodingRTL SynthesisLogic OptimizationPhysical DesignImplemetationCS 150 - Fall 2007 – Lec. #23: Testing - 4TestingHow do I know what that what I designed is really what I got back???Specification to HDLVerification•Formal Verification•Simulation - such as Model SimHDL to LayoutEquivlance testingTool VerificationCS 150 - Fall 2007 – Lec. #23: Testing - 5Why Manufacture Test?How do I know that what I designed is really what I got back???In CS150, we (mostly) trust the FPGA board to work correctly once the design is downloaded. However can we trust that the hardware chip we get will work?CS 150 - Fall 2007 – Lec. #23: Testing - 6Why Manufacture Test?Manufacturing defects can manifest in a variety of ways:Bridging Contaminants Shorts Opens Transistors stuck-open These need to be reduced to models: Single stuck-at-1, stuck-at-0 Multiple stuck-at-1, stuck-at-0 Delay fault models: ・ Gate ・ Path single-stuck-at fault model ubiquitous some use of delay fault modelingCS 150 - Fall 2007 – Lec. #23: Testing - 7Testing of Logic CircuitsFault ModelsTest Generation and CoverageFault DetectionDesign for TestCS 150 - Fall 2007 – Lec. #23: Testing - 8Fault ModelStuck-At ModelAssume selected wires (gate input or output) are “stuck at” logic value 0 or 1Models certain kinds of fabrication flaws that short circuit wires to ground or power, or broken wires that are floatingWire w stuck-at-0: w/0Wire w stuck-at-1: w/1Often assume there is only one fault at a time—even though in real circuits multiple simultaneous faults are possible and can mask each otherObviously a very simplistic model!CS 150 - Fall 2007 – Lec. #23: Testing - 9Fault ModelSimple example:Generate a test case to determine if a is stuck at 1Try 000If a stuck at 1, expect to see f = 0, but see 1 insteadw1w2w3a/1bcdf0000see 1but should be 0CS 150 - Fall 2007 – Lec. #23: Testing - 10Fault ModelSimple examplew1w2w3abcdfTestw1 w2 w3000001010011100101110111a/0XXXa/1XXXb/0Xb/1Xc/0Xc/1Xd/0Xd/1XXXf/0XXXXXf/1XXXFault DetectedTestSetCS 150 - Fall 2007 – Lec. #23: Testing - 11Problems with Fault ModelIn general, n-input circuits require much less than 2n test inputs to cover all possible stuck-at-faults in the circuitHowever, this number is usually still too large in real circuits for practical purposesFinding minimum test cover is an NP-hard problem tooCS 150 - Fall 2007 – Lec. #23: Testing - 12Path SensitizationWire-at-time testing too laboriousBetter to focus on wiring paths, enabling multi-wire testing at the same time“Activate” a path so that changes in signal propagating along the path affects the outputCS 150 - Fall 2007 – Lec. #23: Testing - 13Path SensitizationSimple Example:To activate the path, set inputs so that w1 can influence fE.g., w2 = 1, w3 = 0, w4 = 1 AND gates: one input at 1 passes the other input NOR gates: one input at 0 inverts the other inputTo test: w1 set to 1 should generate f = 0 if path ok faults a/0, b/0, c/1 cause f = 1 w1 set to 0 should generate f = 1 if path ok faults a/1, b/1, c/0 cause f = 0One test can capture several faults at once!w1w2bfcaw3w4101CS 150 - Fall 2007 – Lec. #23: Testing - 14Path SensitizationGood news: one test checks for several faultsNumber of paths much smaller than number of wiresStill an impractically large number of paths for large-scale circuitsPath idea can be used to “propagate” a fault to the output to observe the faultSet inputs and intermediate values so as to pass an internal wire to the output while setting inputs to drive that internal wire to a known valueIf propagated value isn’t as expected, then we have found a fault on the isolated wireCS 150 - Fall 2007 – Lec. #23: Testing - 15Fault Propagationw1w2bfcgw3w4hkw1w2fw3w4b/001111DD00DCS 150 - Fall 2007 – Lec. #23: Testing - 16Fault Propagationw1w2bfcgw3w4hkw1w2fDw3w4g/1110000DDDCS 150 - Fall 2007 – Lec. #23: Testing - 17Tree Structured CircuitsTo test inputs stuck-at-0 at given AND gateSet inputs at other gates to generate AND output of zeroForce inputs at selected gate to generate a oneIf f is 1 then circuit ok, else fault To test inputs stuck-at-1 at given AND gateDrive input to test to 0, rest of inputs driven to 1Other gates driven with inputs that force gates to 0If f is 0 then fault, else OKw1w3w4w2w3w4w1w2w3fCS 150 - Fall


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Berkeley COMPSCI 150 - Testing Methodologies

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