EECS150 Spring 2004 ChipScope Demo Instructions UCB 1 2004 UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE ChipScope Demo Instructions Overview ChipScope is an embedded, software based logic analyzer. By inserting an “intergrated controller core” (icon) and an “integrated logic analyzer” (ila) into your design and connecting them properly, you can monitor any or all of the signals in your design. Even nicer is that ChipScope provides you with a convenient software based interface for controlling the “integrated logic analyzer,” including setting the triggering options and viewing the waveforms. There are six main steps to using ChipScope, as detailed below. 1. Generate an “integrated controller core” or icon 2. Generate one or maybe more “integrated logic analyzers” or ilas 3. Connect the ilas to the icon and make all of these modules part of your design. 4. Synthesize, and implement your design (including the icon and ila) as normal. 5. Program the CaLinx board 6. Run the ChipScope software to access and use the ilas (the ChipScope software requires the icon to gain access to the ilas) Detailed Instructions: Step 1 – Generating the ICON 1. First you will need to start the ChipScope Core Generator a. Go to Start -> All Programs -> ChipScope Pro 6.1i -> ChipScope Core Generator b. This will present you with the ChipScope core generator wizard. 2. Select the “ICON (Integrated Controller)” option and click Next 3. General Options a. You will need to change the Output Netlist location. i. By default ChipScope Core Generator will try and write the output to a directory you are not allowed to modfy. ii. Change the box from “.\icon.edn” to something like “c:\users\cs150-xxx\icon.edn” iii. You MUST include the “icon.edn” at the end of the path. b. Select the VirtexE Device Family c. Select the correct number of Control Ports i. Each ILA requires one control port ii. Normally you will only need 1 Control Port d. Click Next 4. Example Template Options a. Make sure Generate HDL Example Files is Checked i. Select a Verilog example fileEECS150 Spring 2004 ChipScope Demo Instructions UCB 2 2004 ii. Use the Synplicity Synplify synthesis tool b. You do not need to Generate Batch Mode Argument Example Files c. Click Generate Core 5. The ChipScope Pro Core Generator will now generated the ICON core according to the settings you specified. If you have errors go back and make sure you followed the above instructions 6. When you are done click Start Over and proceed directly to step 2 below. Detailed Instructions: Step 2 – Generating the ILA 1. First you will need to start the ChipScope Core Generator if you haven’t already started from the previous section. a. Go to Start -> All Programs -> ChipScope Pro 6.1i -> ChipScope Core Generator b. This will present you with the ChipScope core generator wizard. 2. Select the “ILA (Integrated Logic Analyzer)” option and click Next 3. General Options a. You will need to change the Output Netlist location. i. By default ChipScope Core Generator will try and write the output to a directory you are not allowed to modfy. ii. Change the box from “.\ila.edn” to something like “c:\users\cs150-xxx\ila.edn” iii. You MUST include the “ila.edn” at the end of the path. b. Select the VirtexE Device Family c. Select Rising Edge trigger. i. Falling Edge should only be used by expert debuggers who know EXACTLY what they are doing. d. Click Next 4. Trigger Options a. Normally you will only need 1 Trigger Port i. Set the Trigger Width to any amount you desire (probably either 1bit or 32bits for Lab5) ii. Set the Match Type to Basic unless you need any more advanced features iii. You will most likely need 1 Match Unit iv. Set the Counter Width to Disabled unless you need the counter b. Disable Trigger Sequencing i. This is very useful for more advanced FSM debugging c. Disable the Trigger Output Port d. Click Next 5. Data Options a. Select the desired data depth i. This is the number of samples the ILA will capture after it receives the trigger. It will capture one sample per clock cycle until it captures this many samples. You will probably need relatively few for Lab5.EECS150 Spring 2004 ChipScope Demo Instructions UCB 3 2004 b. Data Same as Trigger should be selected if you are going to connect all the signals you are interested in to the trigger. The bench logic analyzers in the lab have 16bits of input used for both the data and the trigger. The ILA can have separate data and trigger inputs. You may wish to use a one bit trigger connected to a “detected error” signal, or you may wish to simply connect the outputs you are interested in to the trigger port. It is up to you. If you wish to use a “detected error” signal then you should connect that to the trigger and connect the counter output to the data port. Otherwise simple make a very large trigger port and have it be the same as the data. c. Data Width is only available when you are using separate trigger and data ports. Set this to the number of bits you will need to see in the wave window of ChipScope. d. Number of BlockRAMs is simply an indicator of how large the ILA you are making will be. If this number is above 20 you may be doing something incorrect. e. Click Next 6. Example and Template Options a. Make sure Generate HDL Example Files is Checked i. Select a Verilog example file ii. Use the Synplicity Synplify synthesis tool b. You will need to Generate Bus/Signal Name Example File c. You do not need to Generate Batch Mode Argument Example Files d. Click Generate Core 7. The ChipScope Pro Core Generator will now generated the ICON core according to the settings you specified. If you have errors go back and make sure you followed the above instructions 8. When you are done, exit ChipScope Core Generator, you now have all the files you need to begin integrating the logic analyzer into your design. Detailed Instructions: Step 3 – Connecting the Cores to Your Design 1. Declare a control bus for each ILA, similar to the following: a. wire [35:0] ILAControl; b. Remember, each ILA you want to add to your design will require a control bus. c. You can route control busses as input/outputs if you want to instantiate the ICON somewhere other than where you instantiate the ILA. 2.
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