Spring 2009EECS150 - Lec17-timingPage EECS150 - Digital DesignLecture 17 - Combinational Logic CircuitsMarch 17, 2009John Wawrzynek1Finish off Timing FirstSpring 2009EECS150 - Lec17-timingPage Limitations on Clock Rate - Review1Logic Gate Delay2Delays in flip-flops•What must happen in one clock cycle for correct operation?– All signals connected to FF (or memory) inputs must be ready and “setup” before rising edge of clock. – For now we assume perfect clock distribution (all flip-flops see the clock at the same time).2What are typical delay values?Both times contribute to limiting the clock period.Spring 2009EECS150 - Lec17-timingPage In General ...T ≥ τclk→Q + τCL + τsetup3For correct operation:for all paths.• How do we enumerate all paths?– Any circuit input or register output to any register input or circuit output?• Note: – “setup time” for outputs is a function of what it connects to.– “clk-to-q” for circuit inputs depends on where it comes from.Spring 2009EECS150 - Lec17-timingPage CL Delay: Transistors as water valvesIf electrons are water molecules,and a capacitor a bucket ...A “on” p-FET fillsup the capacitor with charge. 1/28/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec3.29Delay Model:CMOS1/28/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec3.30Review: General C/L Cell Delay Model°Combinational Cell (symbol) is fully specified by:•functional (input -> output) behavior-truth-table, logic equation, VHDL•load factor of each input•critical propagation delay from each input to each output for each transition-THL(A, o) = Fixed Internal Delay + Load-dependent-delay x load °Linear model composesCoutVoutCoutDelayVa -> VoutXXXXXXCcriticaldelay per unit loadABX...CombinationalLogic CellInternal Delay1/28/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec3.31Basic Technology: CMOS°CMOS: Complementary Metal Oxide Semiconductor•NMOS (N-Type Metal Oxide Semiconductor) transistors•PMOS (P-Type Metal Oxide Semiconductor) transistors°NMOS Transistor•Apply a HIGH (Vdd) to its gateturns the transistor into a “conductor”•Apply a LOW (GND) to its gateshuts off the conduction path°PMOS Transistor•Apply a HIGH (Vdd) to its gateshuts off the conduction path•Apply a LOW (GND) to its gateturns the transistor into a “conductor”Vdd = 5VGND = 0vVdd = 5VGND = 0v1/28/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec3.32Basic Components: CMOS InverterVddCircuit°Inverter OperationOutInSymbolPMOSNMOSIn OutVddOpenChargeVoutVddVddOutOpenDischargeVinVddVddA “on” n-FET empties the bucket.1/28/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec3.29Delay Model:CMOS1/28/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec3.30Review: General C/L Cell Delay Model°Combinational Cell (symbol) is fully specified by:•functional (input -> output) behavior-truth-table, logic equation, VHDL•load factor of each input•critical propagation delay from each input to each output for each transition-THL(A, o) = Fixed Internal Delay + Load-dependent-delay x load °Linear model composesCoutVoutCoutDelayVa -> VoutXXXXXXCcriticaldelay per unit loadABX...CombinationalLogic CellInternal Delay1/28/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec3.31Basic Technology: CMOS°CMOS: Complementary Metal Oxide Semiconductor•NMOS (N-Type Metal Oxide Semiconductor) transistors•PMOS (P-Type Metal Oxide Semiconductor) transistors°NMOS Transistor•Apply a HIGH (Vdd) to its gateturns the transistor into a “conductor”•Apply a LOW (GND) to its gateshuts off the conduction path°PMOS Transistor•Apply a HIGH (Vdd) to its gateshuts off the conduction path•Apply a LOW (GND) to its gateturns the transistor into a “conductor”Vdd = 5VGND = 0vVdd = 5VGND = 0v1/28/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec3.32Basic Components: CMOS InverterVddCircuit°Inverter OperationOutInSymbolPMOSNMOSIn OutVddOpenChargeVoutVddVddOutOpenDischargeVinVddVdd!"#$%&'())* ++,!-.)'/ 012-)34$5$%&67&1'-)!"#$%&'(#)*(+,%-$*".(/01 2+.$0#$031 4546%,"#$3“1”“0”TimeWater level!"#$%&'())* ++,!-.)'/ 012-)34$5$%&67&1'-)!"#$%&'(#)*(+,%-$*".(/01 2+.$0#$031 4546%,"#$3“0”“1”TimeWater levelThis model is often good enough ...4Spring 2009EECS150 - Lec17-timingPage Gate Delay is the Result of Cascading• Cascaded gates:“transfer curve” for inverter.5Spring 2009EECS150 - Lec17-timingPage Delay in Flip-flops•Setup time results from delay through first latch.•Clock to Q delay results from delay through second latch.clkclk’clkclk’clkclk’clkclk’6Spring 2009EECS150 - Lec17-timingPage Delay and “Fan-out”• The delay of a gate is proportional to its output capacitance. Connecting the output of gate one increases it’s output capacitance. Therefore, it takes increasingly longer for the output of a gate to reach the switching threshold of the gates it drives as we add more output connections.• Driving wires also contributes to fan-out delay.• What can be done to remedy this problem in large fan-out situations?1327Spring 2009EECS150 - Lec17-timingPage Linear Delay Model8Each input adds to output capacitance of previous module.Total output capacitance represented by CTotal delay through the module: T = D + S * C, where D = the delay with no output load S represents the strength of the output drive C = total output capacitance.In reality, different delay from each input to each output, and different for different transitions (0 to 1 versus 1 to 0) on inputs and outputs.This model is hierarchically composable.Spring 2009EECS150 - Lec17-timingPage Searching for processor critical path1600 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 11, NOVEMBER 2001Fig. 1. Process SEM cross section.The process was raised from [1] to limit standby power.Circuit design and architectural pipelining ensure low voltageperformance and functionality. To further limit standby currentin handheld ASSPs, a longer poly target takes advantage of theversus dependence and source-to-body bias is usedto electrically limit transistor in standby mode. All corenMOS and pMOS transistors utilize separate source and bulkconnections to support this. The process includes cobalt disili-cide gates and diffusions. Low source and drain capacitance, aswell as 3-nm gate-oxide thickness, allow high performance andlow-voltage operation.III. ARCHITECTUREThe microprocessor contains 32-kB instruction and datacaches as well as an eight-entry coalescing writeback buffer.The instruction and data cache
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