Spring 2003 EECS150 – Lec28-FFsPage 1EECS150 - Digital DesignLecture 28 – More Flip-flopsMay 1, 2003John WawrzynekSpring 2003 EECS150 – Lec28-FFsPage 2Cross-coupled NOR gates• If both R=0 & S=0, then cross-couped NORsequivalent to a stable latch:• If either R or S becomes =1 then state may change:• What happens if R or S or both become = 1?RS NOR00 101 010 011 0remember,RSQQ'01000110Spring 2003 EECS150 – Lec28-FFsPage 3Asynchronous State Transition DiagramQQ'01QQ'10QQ'00?SR=00 SR=00SR=10SR=01SR=11SR=01SR=11SR=10SR=00SR=10SR=01SR Latch:SR Q00 hold01 010 111 indeterminate• S is “set” input• R is “reset” inputQQ’=00 is often called a “forbidden state”Spring 2003 EECS150 – Lec28-FFsPage 4Nand-gate based SR latch• Same behavior as cross-coupled NORs with invertered inputs.Spring 2003 EECS150 – Lec28-FFsPage 5Level-sensitive SR Latch• The input “C” works as an “enable” signal, latch only changes output when C is high.• usually connected to clock.• Generally, it is not a good idea to use a clock as a logic signal (into gates etc.). This is a special case.Spring 2003 EECS150 – Lec28-FFsPage 6D-latchCompare to transistor version:Spring 2003 EECS150 – Lec28-FFsPage 7Flip-flopsSpring 2003 EECS150 – Lec28-FFsPage 8J-K FFJ K Q(t) Q(t+∆)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0holdresetsettoggle• Add logic to eliminate “indeterminate” action of RS FF.• New action is “toggle”•J = “jam”• K = “kill”JKQclkSpring 2003 EECS150 – Lec28-FFsPage 9J-K Flip-flop from D-FFSpring 2003 EECS150 – Lec28-FFsPage 10Toggle Flip-flop from D-FFSpring 2003 EECS150 – Lec28-FFsPage 11Storage Element Taxonomysynchronous asynchronouslevel-sensitive edge-triggeredD-type Ë 9 n.a.JK-type n.a. 9 n.a.RS-type 99 Ë“latch” “flip-flop” “latch”Ë“natural” form9 “possible” formSpring 2003 EECS150 – Lec28-FFsPage 12Design Example with RS FF• With D-type FF state elements, new state is computed based on inputs & present state bits - reloaded each cycle.• With RS (or JK) FF state elements, inputs are used to determine conditions under which to set or reset state bits.• Example: bit-serial adder (LSB first)n-bit shift registern-bit shift registersscresetRFAFFBAWith D-FF for carrySpring 2003 EECS150 – Lec28-FFsPage 13Bit-serial adder with RS FF• RS FF stores the carry:SRQab0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1a b cici+1sCarry kill a’b’Carry
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