Spring 2003 EECS150 - Lec29-asynchPage 1EECS150 - Digital DesignLecture 29 - Asynchronous Sequential CircuitsMay 6, 2003John WawrzynekSpring 2003 EECS150 - Lec29-asynchPage 2Outline• SynchronizersFigures from “Digital Design”, John F. WakerlyPrentice Hall, 2000An excellent treatment of the topic.• Purely asynchronous circuits– “self-timed” circuits– Mano has another class of asynchronous circuits (not covered in class)Spring 2003 EECS150 - Lec29-asynchPage 3Asynchronous Inputs to Synchronous Systems• Many synchronous systems need to interface to asynchronous input signals:– Consider a computer system running at some clock frequency, say 1GHz with:• Interrupts from I/O devices, keystrokes, etc.• Data transfers from devices with their own clocks– Ethernet has its own 100MHz clock– PCI bus transfers, 66MHz standard clock.– These signals could have no known timing relationship with the system clock of the CPU.Spring 2003 EECS150 - Lec29-asynchPage 4“Synchronizer” Circuit• For a single asynchronous input, we use a simple flip-flop to bring the external input signal into the timing domain of the system clock:• The D flip-flop samples the asynchronous input at each cycle and produces a synchronous output that meets the setup time of the next stage.Spring 2003 EECS150 - Lec29-asynchPage 5“Synchronizer” Circuit• It is essential for asynchronous inputs to be synchronized at only one place. • Two flip-flops may not receive the clock and input signals at precisely the same time (clock and data skew). • When the asynchronous changes near the clock edge, one flip-flop may sample input as 1 and the other as 0.Spring 2003 EECS150 - Lec29-asynchPage 6“Synchronizer” Circuit• Single point of synchronization is even more important when input goes to a combinational logic block (ex. FSM)• The CL block can accidentally hide the fact that the signal is synchronized at multiple points.• The CL magnifies the chance of the multiple points of synchronization seeing different values.• Sounds simple, right?Spring 2003 EECS150 - Lec29-asynchPage 7Synchronizer Failure & Metastability• We think of flip-flops having only two stable states - but all have a third metastable state halfway between 0 and 1.• When the setup and hold times of a flip-flop are not met, the flip-flop could be put into the metastable state. • Noise will be amplified and push the flip-flop one way or other.• However, in theory, the time to transition to a legal state is unbounded.• Does this really happen?• The probability is low, butthe number of trials is high!Spring 2003 EECS150 - Lec29-asynchPage 8Synchronizer Failure & Metastability• If the system uses a synchronizer output while the output is still in the metastable state ⇒ synchronizer failure.• Initial versions of several commercial ICs have suffered from metastability problems - effectively synchronization failure:– AMD9513 system timing controller– AMD9519 interrupt controller– Zilog Z-80 Serial I/O interface– Intel 8048 microprocessor– AMD 29000 microprocessor• To avoid synchronizer failure wait long enough before using a synchronizer’s output. “Long enough”, according to Wakerly, is so that the mean time between synchronizer failures is several orders ofmagnitude longer than the designer’s expected length of employment!• In practice all we can do is reduce the probability of failure to a vanishing small value.Spring 2003 EECS150 - Lec29-asynchPage 9Reliable Synchronizer Design• The probability that a flip-flop stays in the metastable state decreases exponentially with time. • Therefore, any scheme that delays using the signal can be used to decrease the probability of failure. • In practice, delaying the signal by a cycle is usually sufficient:• If the clock period is greater than metastability resolution time plus FF2 setup time, FF2 gets a synchronized version of ASYNCIN.• Multi-cycle synchronizers (using counters or more cascaded flip-flops) are even better – but often overkill.Spring 2003 EECS150 - Lec29-asynchPage 10Purely Asynchronous Circuits• Many researchers (and a few industrial designers) have proposed a variety of circuit design methodologies that eliminate the need for a globally distributed clock. • They cite a variety of important potential advantages over synchronous systems (will list later).• To date, these attempts have remained mainly in Universities.• A few commercial asynchronous chips/systems have been build.• Sometimes, asynchronous blocks sometimes appear inside otherwisesynchronous systems.• Asynchronous techniques have long been employed in DRAM and other memory chips for generation internal control without external clocks. (Precharge/sense-amplifier timing based on address line changes.)• These techniques are generally interesting, and if nothing else help put synchronous design in perspective.Spring 2003 EECS150 - Lec29-asynchPage 11Synchronous Data Transfer• In synchronous systems, the clock signal is used to coordinate the movement of data around the system. • If we are going to eliminate the clock, we need to substitute some technique for managing the flow of data.• Take for example, transferring data across a bus:• By design, the clock period is sufficiently long to accommodate wire delay and time to get the data into the receiver.receiversenderclockdataSpring 2003 EECS150 - Lec29-asynchPage 12Delay Insensitive (self-timed transfer)• Request/acknowledge “handshake” signal pair used to coordinate data transfer.4-cycle (“return-to-zero”) signaling• Note, transfer is insensitive to any delay in sending and receiving. sender receiverdatarequestacknowledgedatarequestacknowledgeHello, here’s some dataThanks, I got itYou’re welcomeSee you laterSpring 2003 EECS150 - Lec29-asynchPage 13Delay Insensitive (self-timed transfer)2-cycle (“non-return-to-zero”) signaling• Only two transitions per transfer. Maybe higher performance.• More complex logic. 4-cycle return to zero can usually be overlapped with other operations.sender receiverdatarequestacknowledgedatarequestacknowledgeSpring 2003 EECS150 - Lec29-asynchPage 14Self-timed Processing• Of course, a processing elements can be inserted. Req signal starts it, and it generates a “completion” (ack) signal when its output data is ready.• The output ack becomes the request for the receiver or next stage:• Note, three cascaded CL blocks
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