1Good Design & Network Audio10/3/2008 EECS150 Lab Lecture #6 1EECS150 Fall2008 - Lab Lecture #6Chris FletcherAdopted from slides designed by Greg Gibeling and Chris Fletcher10/3/2008 EECS150 Lab Lecture #6 2Today (1) Good Design FSMs: The Good, Bad and Ugly Interfaces (Part 1) Signal Conditioning Administrative Info10/3/2008 EECS150 Lab Lecture #6 3Today (2) Lab #6: Network Audio Motivation Network Organization Ethernet Packets Eth2Audio Async FIFO210/3/2008 EECS150 Lab Lecture #6 4Finite State Machines (1) After all we have told you…FSMs seldom lead to efficient circuits The Real Story When they are not useful When they are useful How you can tell between the two cases10/3/2008 EECS150 Lab Lecture #6 5Finite State Machines (2) Most FSMs look like… Important properties Straight path No complicated branching logic10/3/2008 EECS150 Lab Lecture #6 6Finite State Machines (3) It’s a ring counter! Bubble-Arc diagrams don’t necessitate the FSM design pattern310/3/2008 EECS150 Lab Lecture #6 7Finite State Machines (4) Conclusion Think simple A counter is an incredibly powerful circuit On the other hand… Some FSMs look like…(await the very necessary page turn)10/3/2008 EECS150 Lab Lecture #6 8Look any different?Complex branching!10/3/2008 EECS150 Lab Lecture #6 9Finite State Machines (6) Do not use FSMs when you have… Few branches Linear transitions Use FSMs when you have… Many branches Complicated decision logic Conditional transitions410/3/2008 EECS150 Lab Lecture #6 10Signal Conditioning (1) Off-by-a-cycle Errors Shorten a Pulse Lengthen a Pulse Shift a Pulse Adaptors between complex modules Simple modification outside module Don’t/Can’t touch module internally10/3/2008 EECS150 Lab Lecture #6 11Signal Conditioning (2) Shorten a Pulse 5 Cycles -> 4 Cycles Any guesses? What if we delayed the input?InOut10/3/2008 EECS150 Lab Lecture #6 12Signal Conditioning (3) Shorten a Pulse Out = In & In_DelayedInOutIn_DelayedRegIn_DelayedInOut510/3/2008 EECS150 Lab Lecture #6 13Signal Conditioning (4) Lengthen a Pulse Out = In | In_DelayedInOutIn_DelayedRegIn_DelayedInOut10/3/2008 EECS150 Lab Lecture #6 14Administrative Info Project starts next friday: 10/10 Digital Oscilloscope! Commit to your partner The first checkpoint is 1 week long SVN Repositories Will be online at the end of next week Version-control tutorial on the way10/3/2008 EECS150 Lab Lecture #6 15Lab #6: Network Audio Play Audio off Ethernet Receive Ethernet packets Decode and remove header Filter packets Play audio data payload A Major Project by Itself Given: Ethernet, Audio, ETC To be written: Packet Decode & Filtering610/3/2008 EECS150 Lab Lecture #6 16Lab #6: Network Audio Your project and Lab 6 Audio Ethernet Waveform Stream audio into oscilloscope Audio Visualizations10/3/2008 EECS150 Lab Lecture #6 17Network Organization (1)Audio StreamWHITE (0)TA StationCaLinx2 CaLinx2 CaLinx2 CaLinx2 CaLinx2 CaLinx2 CaLinx210/3/2008 EECS150 Lab Lecture #6 18Network Organization (2)DO NOT MODIFY THE PRODUCTION NETWORK710/3/2008 EECS150 Lab Lecture #6 19Ethernet Packets (1) We’re using raw Ethernet No TCP/IP, its too complex Cant use this on the internet Raw Ethernet: 48bit Destination MAC Address 48bit Source MAC Address 16bit Ethernet Type Payload 32bit CRC10/3/2008 EECS150 Lab Lecture #6 20Ethernet Packets (2)Destination [47:16]32bitsDestination [15:0] Source [47:32]Source [31:0]Ethernet Type [15:0] Reserved [15:0]PCM Audio Data Sample 0 [31:0]PCM Audio Data Sample 1023 [31:0]1028words0xFFFFFFFF32bits0xFFFF 0x00900xc2001c500x0101 0x????PCM Audio Data Sample 0 [31:0]PCM Audio Data Sample 1023 [31:0]Ethernet Packet Format Broadcast Audio Packet1024wordsCRC [31:0]10/3/2008 EECS150 Lab Lecture #6 21Ethernet Packets (3) A Good Packet Total: 1028x 32bit Words 48bit Destination (0xFFFFFFFFFFFF) 48bit Source (0x0090c2001c50) 16bit Packet Type (0x0101) 16bit Padding (0x????) 1024x 32bit PCM Audio Data810/3/2008 EECS150 Lab Lecture #6 22Ethernet Packets (4) A Bad Packet Who knows how long? Source and Destination could be anything Packet Type probably not 0x0101 Coping with bad packets Do NOT send them to AudioTop Just keep dropping data until end of packet Done Signal: InPacketValid & InPacketInvalid10/3/2008 EECS150 Lab Lecture #6 23Lab #6: Eth2Audio (1)AP_BIT_CLOCK (12MHz)RegisterMAC Rx UnitEth Rx UnitInput Shift RegisterOutput Shift RegisterAC97 ControllerLM4549A CodecPHY_RX_CLK (~25MHz)LXT975 Ethernet PHY4bit Raw Ethernet Data4bit Raw Ethernet Data~25MHz Ethernet Clock32b Ethernet Packet Data32b PCM Audio DataAP_SDATA_OUT AP_SDATA_INReceive Block DiagramAsync FIFO32Eth2AudioDecode & Filter32b PCM Audio Data10/3/2008 EECS150 Lab Lecture #6 24Lab #6: Eth2Audio (2)Signal Width Dir DescriptionDIn32 I Data from MAC_TopInValid1 I Indicates DIn is validInPacketValid1 I Indicates the end of a good(crc) packetInPacketInvalid1 I Indicates the end of a bad(crc) packetEthernetClock1 I 25MHz Ethernet ClockEthernetReset1 I EthernetClock sync. ResetAudioClock1 I 12.288MHz Audio ClockAudioReset1 I AudioClock sync. ResetDOut32 O Data out to AudioTopOutRequest1 I AudioTop requesting a new wordOutValid1 O Indicates DOut is valid910/3/2008 EECS150 Lab Lecture #6 25Lab #6: Async FIFO (3) Buffer to match two data rates Great for data path clock domain crossings Write on one clock (WR_) Read on another (RD_) Good place to buffer audio10/3/2008 EECS150 Lab Lecture #6 26Lab #6: Eth2Audio (4) Design No FSMs allowed Word Counter How many bits wide? Valid Register Stores whether the packet is valid or not Reset When do you reset word counter and valid register?10/3/2008 EECS150 Lab Lecture #6 27Lab #6: Eth2Audio (5) Testing We give you a very nice testbench Read Lab5Testbench.v Read Lab5TestPackets.txt Fix your module in simulation You can use ChipScope w/ 1 clock Checkoff We should hear nice clean audio Show us your module using
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