19/19/2008 EECS150 Lab Lecture #4 1DebuggingEECS150 Fall2008 - Lab Lecture #4Sarah SwisherAdopted from slides designed by Greg Gibeling9/19/2008 EECS150 Lab Lecture #4 2Today (1) Lab #2 Solution Simulation vs Hardware Debugging Goals Tips Algorithm Administrative Info9/19/2008 EECS150 Lab Lecture #4 3Today (2) Lab #4 Bottom Up Testing (Peak Detector) Designing Test Hardware (Broken Adder) Exhaustive FSM Testing (Broken FSM) Kramnik29/19/2008 EECS150 Lab Lecture #4 4module Accumulator(In, Out, Enable, Clock, Reset);input [7:0] In;output [7:0] Out;input Enable;input Clock, Reset;reg [7:0] Out;always @ (posedge Clock) beginif (Reset) Out <= 8'h00; else if (Enable) Out <= Out + In; endendmoduleLab #2 Solution (1)9/19/2008 EECS150 Lab Lecture #4 5Lab #2 Solution (2)and1not1or1In0In1EqualInGreaterInGreaterOutand2xor1not3not2EqualOut9/19/2008 EECS150 Lab Lecture #4 6Lab #2 Solution (3) Accumulator Simple, easy to build What is the actual circuit? Get used to answering this in your head RTL View from Lab #1 (Section 5.3 Synthesis) Peak Detector Hard to build Minute control of hardware Tools couldn’t optimize though!!39/19/2008 EECS150 Lab Lecture #4 7Simulation vs. Hardware (1) Debugging in Simulation Slow Running Time Fast Debugging Waveforms Text messages Full Visibility Can examine any signal Easy to Fix A few minutes to compile and resimulate9/19/2008 EECS150 Lab Lecture #4 8Simulation vs. Hardware (2) Debugging in Hardware Fast Running Time Full speed in fact Slow Debugging Synthesis can take hours Little or No Visibility Very hard to probe signals Maybe Impossible to Fix (ASICs)9/19/2008 EECS150 Lab Lecture #4 9Simulation vs. Hardware (3) Simulation Functional Testing & Verification Test everything at least minimally Fully Verify what you can This will save you many sleepless nights Hardware Debugging Treat this as a last resort It is painful49/19/2008 EECS150 Lab Lecture #4 10Debugging (1) Debugging Algorithm Hypothesis: What’s broken? Control: Give it controlled test inputs Expected Output: What SHOULD it do? Observe: Did it work right? If it broke: THAT’S GREAT! If we can’t break anything like this then the project must be working…9/19/2008 EECS150 Lab Lecture #4 11Debugging (2) Don’t debug randomly Just changing things at random often makes things look fixed It won’t really help Debug systematically Your first design may be the best “1000 CS150 students at a 1000 typewriters…” What can you do?9/19/2008 EECS150 Lab Lecture #4 12Debugging (3) High Level Debugging Localize the problem N64? SDRAM? Video? Test Patterns Lets you easily isolate the broken component If you know exactly what’s going in you can check what’s coming out59/19/2008 EECS150 Lab Lecture #4 13Debugging (4) Simulate the broken component(s) Writing test benches takes less time than sitting around wondering why its broken Everyone hates writing testbenches (Even me) Get used to it9/19/2008 EECS150 Lab Lecture #4 14Debugging (5) Your best debugging tool is logic If 3 out of 4 components work, what’s broken? Question all your assumptions! What you think is true isn’t really true Don’t debug the wrong problem Know how modules you interface with behave9/19/2008 EECS150 Lab Lecture #4 15Debugging (6) Before you change anything Understand exactly what the problem is Find an efficient solution Evaluate alternative solutions After the change Fixes may make things worse sometimes May uncover a second bug May be an incorrect fix Repeat the debugging process69/19/2008 EECS150 Lab Lecture #4 16Debugging (7) Ask around Someone else may have had the same bug They’ll probably at least know about where the problem is Different bugs may produce the same results TAs The TAs know common problems We’re here to help, not solve it for you9/19/2008 EECS150 Lab Lecture #4 17Administrative Info Partners You MUST have one for this week Try someone other than your best friend Restrictions You can change partners until the project starts You must be in the same lab Project in 3 weeks9/19/2008 EECS150 Lab Lecture #4 18Part1: Bottom Up Testing (1)What if EqualOut = 1’b0 and GreaterOut = 1’b0?Lab4Comp1EqualIni+1GreaterIni+1AiBiEqualOutiGreaterOutiA=BA<B79/19/2008 EECS150 Lab Lecture #4 19Part1: Bottom Up Testing (2) Exhaustive Testing Ideal Testing Method Circuit is 100% tested! Requires us to test a LOT! Can we do it here? (24possible inputs) Method Make a truth table Have the testbench generate all inputs Make sure outputs math truth table9/19/2008 EECS150 Lab Lecture #4 20Part1: Bottom Up Testing (3)EqualOut[3]GreaterOut[3]EqualOut[2]GreaterOut[2]EqualOut[1]GreaterOut[1]A[0] B[0]GreaterEqualLab4Comp4Lab4Comp1Lab4Comp1Lab4Comp1Lab4Comp1A[1] B[1]A[2] B[2]A[3] B[3]9/19/2008 EECS150 Lab Lecture #4 21Part1: Bottom Up Testing (4) Exhaustive Testing? 28= 256 Possible Inputs Method Use a for loop to generate all inputs Loops allowed only in testbenches They will not synthesize Compare against a “>=“ Print a message if they differ89/19/2008 EECS150 Lab Lecture #4 22Part1: Bottom Up Testing (5)RegisterLab4PeakDetectorInClockOutReset≥44449/19/2008 EECS150 Lab Lecture #4 23Part1: Bottom Up Testing (6) Exhaustive Testing? 24= 16 Possible Inputs 24= 16 Possible States 16*16 = 256 combinations We could do it in this case Can’t exhaustively test FSMs Too many state/input combinations Must rely on directed testing9/19/2008 EECS150 Lab Lecture #4 24initial beginendPart1: Bottom Up Testing (7)integer i;reg [3:0] TestValues[1:16];$readmemh("TestValues.txt", TestValues);for(i = 1; i <= 16; i = i + 1) begin#(`Cycle);In = TestValues[i]; $display("In = %d, Peak = %d", In, Peak);end99/19/2008 EECS150 Lab Lecture #4 25Part1: Bottom Up Testing (8) Read Test Vectors from a File Designing Test Vectors Make sure to cover most cases We want 95%+ coverage Designing test vectors is a “black art” $ Processes Not synthesizeable More information in IEEE Verilog Reference9/19/2008 EECS150 Lab Lecture #4 26Part2: Test Hardware (1)Lab4 Part2 AdderTestControlABSumABSumErrorRunningGoResetLab4Part2Tester9/19/2008 EECS150 Lab Lecture #4
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