EECS 150 - Components and Design Techniques for Digital SystemsLec 15 – Addition, Subtraction, and Negative Numbers David CullerElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www.eecs.berkeley.edu/~cullerhttp://inst.eecs.berkeley.edu/~cs15010/16/2007 EECS150-Fa07 L15 additionOverview•Recall basic positional notation•Binary AdditionFull Adder (Boolean Logic Revisited)• Ripple Carry• Carry-select adder• Carry lookahead adder•Binary Number RepresentationSign & Magnitude, Ones Complement, Twos Complement10/16/2007 EECS150-Fa07 L15 additionManipulating representations of numbers• Example (from 2ndgrade)• Sequence of decimal digits (radix 10)• Position represents significance (most -> least)• Carry into next position• 3-to-2 conversion at each step• Results may be one digit longer, but assumed you could “make room” for it5396+47251121110110/16/2007 EECS150-Fa07 L15 additionPositional Notation• Sequence of digits: Dk-1Dk-2…D0represents the valueDk-1Bk-1+ Dk-2Bk-2+ …+ D0B0 where Di ∈ { 0, …, B-1 }• B is the “base” or “radix” of the number system• Example: 200410, • Can convert from any radix to any other– 11012= 1310 = 0D16– 1CE816= 1·163+ 12·162+ 14·161+ 8·160= 740010– 4368= 4·82 + 3·81 + 6·80 = 2861010/16/2007 EECS150-Fa07 L15 additionComputer Number Systems• We all take positional notation for granted– Dk-1Dk-2…D0represents Dk-1Bk-1+ Dk-2Bk-2+ …+ D0B0 where B ∈ { 0, …, B-1 }• We all understand how to compare, add, subtract these numbers– Add each position, write down the position bit and possibly carry to the next position• Computers represent finite number systems– Generally radix 2• How do they efficiently compare, add, sub?– How do we reduce it to networks of gates and FFs?• Where does it break down?– Manipulation of finite representations doesn’t behave like same operation on conceptual numbers10/16/2007 EECS150-Fa07 L15 additionUnsigned Numbers - Addition0000011100111011111111101101110010101001100001100101010000100001+0+1+2+3+4+5+6+7+8+9+10+11+12+13+14+15+Example: 3 + 2 = 5Unsigned binary additionIs just addition, base 2Add the bits in each position and carry0 0 1 1+ 0 0 1 00 1 0 11How do we build a combinational logic circuit to perform addition?=> Start with a truth table and go from there10/16/2007 EECS150-Fa07 L15 additionBinary Addition: Half AdderAi 0 0 1 1Bi 0 1 0 1Sum 0 1 1 0Carry 0 0 0 1AiBi01010110Sum = Ai Bi + Ai Bi= Ai + BiAiBi01010010Carry = Ai BiHalf-adder SchematicCarry Sum A i B i But each bit position may have a carry in…10/16/2007 EECS150-Fa07 L15 additionFull-Adder (derivation)S = CI xor A xor BCO = B CI + A CI + A B = CI (A + B) + A B0 0 1 1+ 0 0 1 00 1 0 11ABSCinCo0 1 1 0 1 0 0 10 0 0 1 0 1 1 1A 0 0 0 0 1 1 1 1B 0 0 1 1 0 0 1 1CI 0 1 0 1 0 1 0 1S CO A BCI0100 01 11 1001101001A BCI0100 01 11 1000010111SCOFA3 unaryinputs2 binaryoutputs010/16/2007 EECS150-Fa07 L15 additionFull AdderAABBCI COABCISABCiSCoNow we can connect them up to do multiple bits…10/16/2007 EECS150-Fa07 L15 additionRipple Carry+A0 B0S0C1+A3 B3S3+A2 B2S2+A1 B1S1C2C3S4 ?10/16/2007 EECS150-Fa07 L15 additionFull Adder from Half Adders (little aside)Alternative Implementation: 5 GatesA B + CI (A xor B) = A B + B CI + A CIStandard Approach: 6 GatesAAABBBCICISCOHalf AdderABHalf AdderA + BCIA + B + CISSCOCOCI (A + B)A BSCO10/16/2007 EECS150-Fa07 L15 additionDelay in the Ripple Carry AdderCritical delay: the propagation of carry from low to high order stagesAABBCICO@0@0@0@0@N@1@1@N+1@N+2latearrivingsignaltwo gate delaysto compute CO4 stageadderfinal sum andcarryA 0 B 0 C 0 S 0 @2 A 1 B 1 C 1 @2 S 1 @3 A 2 B 2 C 2 @4 S 2 @5 A 3 B 3 C 3 @6 S 3 @7 C 4 @8 0 1 2 310/16/2007 EECS150-Fa07 L15 additionRipple Carry TimingCritical delay: the propagation of carry from low to high order stages1111 + 0001worst caseadditionT0: Inputs to the adder are validT2: Stage 0 carry out (C1)T4: Stage 1 carry out (C2)T6: Stage 2 carry out (C3)T8: Stage 3 carry out (C4)2 delays to compute sumbut last carry not readyuntil 6 delays laterT0 T2 T4 T6 T8S0, C1 ValidS1, C2 Valid S2, C3 Valid S3, C4 Valid10/16/2007 EECS150-Fa07 L15 additionRecall: Virtex-E CLBCLB = 4 logic cells (LC) in two slicesLC: 4-input function generator, carry logic, storage ele’t80 x 120 CLB array on 2000E16x1 synchronous RAMFF or latch10/16/2007 EECS150-Fa07 L15 additionAdders (cont.)Ripple AdderRipple adder is inherently slow because, in generals7 must wait for c7 which must wait for c6 …T α n, Cost α nHow do we make it faster, perhaps with more cost?FAc0a0b0s0c1c2c3c4c5c6c7s7 s6Or use a MUX !!!Classic approach: Carry Look-Ahead10/16/2007 EECS150-Fa07 L15 additionCarry Select AdderT = Tripple_adder/ 2 + TMUXCOST = 1.5 * COSTripple_adder+ (n+1) * COSTMUX01c8FA0a4a5a6a7b7 b6 b5 b4c0a0b0s0a1a2a3b3 b2 b1s1s2s3FA1a4a5a6a7b7 b6 b5 b410 1010 10s4s5s6s710/16/2007 EECS150-Fa07 L15 additionExtended Carry Select Adder• What is the optimal # of blocks and # of bits/block?– If # blocks too large delay dominated by total mux delay– If # blocks too small delay dominated by adder delay per block101 0 1 0 1 0 1 04-bit Adder 4-bitAdder101 0 1 0 1 0 1 04-bit Adder 4-bitAdder101 0 1 0 1 0 1 04-bit Adder 4-bitAdder4-bit Addera3-a0b3-b0cincouta11-a8b11-b8a15-a12b15-b12 b7-b4 a7-a4bits N of stages NT α sqrt(N),Cost ≈2*ripple + muxes10/16/2007 EECS150-Fa07 L15 additionCarry Select Adder Performance• Compare to ripple adder delay:Ttotal= 2 sqrt(N) TFA –TFA, assuming TFA= TMUXFor ripple adder Ttotal= N TFA“cross-over” at N=3, Carry select faster for any value of N>3.• Is sqrt(N) really the optimum?– From right to left increase size of each block to better match delays– Ex: 64-bit adder, use block sizes [12 11 10 9 8 7 7]• How about recursively defined carry select?101 0 1 0 1 0 1 04-bit Adder 4-bitAdder101 0 1 0 1 0 1 04-bit Adder 4-bitAdder101 0 1 0 1 0 1 04-bit Adder 4-bitAdder4-bit Addera3-a0b3-b0cincouta11-a8b11-b8a15-a12b15-b12 b7-b4 a7-a410/16/2007 EECS150-Fa07 L15 additionAnnouncements• Reading Katz 5.6 and Appendix A• Mid III will just stay put in final slot – no more fussing with it.• Project demo at Lab Lecture friday• Don’t hedge on lab workload reporting– It matters to us and is NOT a negative in your grade• Lab5 | CP1 | CP2 crunch– It should lighten– Don’t hesitate to get guidance on the specifics of your approach from the TAs. They are there to help.–
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