1Fall 2011 EECS150 Lecture 10Page 1EECS150 - Digital DesignLecture 10 – SRAM (I)September 27, 2011Elad AlonElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www-inst.eecs.berkeley.edu/~cs150Fall 2011 EECS150 Lecture 10Page 2Announcements• Homework #4 due Thursday• Homework #5 out Thursday– Due next Thurs.2Fall 2011 EECS150 Lecture 10Page 3Project CPU Pipelining Review• Pipeline rules: – Writes/reads to/from DMem use leading edge of “M”– Writes to RegFile use trailing edge of “M”– Instruction Decode and Register File access is up to you.• 1 Load Delay Slot, 1 Branch Delay Slot– No Stalling may be used to accommodate pipeline hazards (in final version).•Other:– Target frequency to be announced later (50-100MHz)– Minimize cost– Posedge clocking onlyIXMinstruction fetchexecute access data memory3-stage pipelineFall 2011 EECS150 Lecture 10Page 4Memory-Block Basics• Uses:Whenever a large collection of state elements is required.– data & program storage – general purpose registers – data buffering – table lookups – CL implementation •Basic Types:– RAM - random access memory –ROM -read only memory – EPROM, FLASH - electrically programmable read only memory M X N memory:Depth = M, Width = N.M words of memory, each word N bits wide.log2(M)3Fall 2011 EECS150 Lecture 10Page 5Memory Components Types:•Volatile:– Random Access Memory (RAM): • SRAM "static"• DRAM "dynamic"• Non-volatile:– Read Only Memory (ROM): • Mask ROM "mask programmable" • EPROM "electrically programmable" • EEPROM "erasable electrically programmable" • FLASH memory - similar to EEPROM with programmer integrated on chipAll these types are available as stand alone chips or as blocks in other chips.Focus in ~2 weeksFocus todayFall 2011 EECS150 Lecture 10Page 6Standard Internal Memory Organization • RAM/ROM naming convention: – examples: 32 X 8, "32 by 8" => 32 8-bit words – 1M X 1, "1 meg by 1" => 1M 1-bit words 2-D arrary of bit cells. Each cell stores one bit of data.Special circuit tricks are used for the cell array to improve storage density.4Fall 2011 EECS150 Lecture 10Page 7Address DecodingFall 2011 EECS150 Lecture 10Page 8SRAM InternalsWL1WL2WLi5Fall 2011 EECS150 Lecture 10Page 9SRAM Cell DetailsBLBLWL• Most common is 6 transistors (6T) cell:• Notice: no explicit read vs. write signal– WL activates the cell (and all others on same column) for both operations– Will see shortly how to distinguish reads from writesFall 2011 EECS150 Lecture 10Page 10SRAM Cell ArrayWL2WL0WL3BLBL_BWL2WL0WL3BLBL_B6Fall 2011 EECS150 Lecture 10Page 11SRAM Cell Array: WriteFor write operation, column bit lines are driven differentially (e.g., 0 on BL, 1 on BL_b). Values overwrite cell state.Fall 2011 EECS150 Lecture 10Page 12SRAM Cell Array: ReadFor read operation, column bit lines are both driven to high voltage (supply), then released. When activated, cell pulls down one bit line or the other.7Fall 2011 EECS150 Lecture 10Page 13Column Multiplexing: • Permits input/output data widths different from row width.•Enables physical aspect ratio closer to a square– Why is this important?Technique illustrated for read operation. Similar approach for write.1024x1:256x4:Fall 2011 EECS150 Lecture 10Page 14Logical View: Cascading Memory-BlocksHow to make larger memory blocks out of smaller ones.Increasing the width. Example: given 1Kx8, want 1Kx168Fall 2011 EECS150 Lecture 10Page 15Logical View: Cascading Memory-BlocksHow to make larger memory blocks out of smaller ones.Increasing the depth. Example: given 1Kx8, want 2Kx8Fall 2011 EECS150 Lecture 10Page 16Multi-ported Memory• Motivation:– Consider CPU core register file:• 1 read or write per cycle limits processor performance.• Complicates pipelining. Difficult for different instructions to simultaneously read or write regfile.• Common arrangement in pipelined CPUs is 2 read ports and 1 write port.– I/O data buffering:• Dual-porting allows both sides to simultaneously access memorydatabufferdisk or network interfaceCPUAaDinaWEaAbDinbWEbDual-portMemoryDoutaDoutb9Fall 2011 EECS150 Lecture 10Page 17Dual-ported Memory Internals• Add decoder, another set of read/write logic, bit lines, word lines:• Example cell: SRAM• Repeat everything but cross-coupled inverters.• This scheme extends up to a couple more ports, then need to add additional transistors.decadecbcellarrayr/w logicr/w logicdata portsaddressportsb2b2b1b1WL2WL1Fall 2011 EECS150 Lecture 10Page 18Adding Ports to Primitive Memory BlocksAdding a read port to a simple dual port (SDP) memory.Example: given 1Kx8 SDP, want 1 write & 2 read ports.10Fall 2011 EECS150 Lecture 10Page 19Adding Ports to Primitive Memory BlocksHow to add a write port to a simple dual port memory.Example: given 1Kx8 SDP, want 1 read & 2 write ports.Fall 2011 EECS150 Lecture 10Page 20Virtex-5 LX110T memory blocks: Block RAMs in four columns.Distributed RAM using LUTs among the CLBs.11Fall 2011 EECS150 Lecture 10Page 21SLICEL vs SLICEM ...SLICEMSLICELSLICEM adds memory features to LUTs, + muxes.Fall 2011 EECS150 Lecture 10Page 22A SLICEM 6-LUT…12Fall 2011 EECS150 Lecture 10Page 23Example Distributed RAM (LUT RAM) Example configuration: Single-port 256b x 1,registered output.A 128 x 32b LUT RAM has a 1.1ns access time.Fall 2011 EECS150 Lecture 10Page 24Distributed RAM PrimitivesAll are built from a single slice or less.Remember, though, that the SLICEM LUT is naturally only 1 read and 1 write port.13Fall 2011 EECS150 Lecture 10Page 25Example Dual Port ConfigurationsFall 2011 EECS150 Lecture 10Page 26Distributed RAM Timing14Fall 2011 EECS150 Lecture 10Page 27Spring 2009EECS150 - Lec03-FPGAPage Fall 2011 EECS150 Lecture 10Page 28Block RAM Overview• 36K bits of data total, can be configured as: – 2 independent 18Kb RAMs, or one 36Kb RAM. • Each 36Kb block RAM can be configured as: – 64Kx1 (when cascaded with an adjacent 36Kb block RAM), 32Kx1, 16Kx2, 8Kx4, 4Kx9, 2Kx18, or 1Kx36 memory. • Each 18Kb block RAM can be configured as:– 16Kx1, 8Kx2, 4Kx4, 2Kx9, or 1Kx18 memory. • Write and Read are synchronous operations.• The two ports are symmetrical and totally independent (can have different clocks), sharing only the stored data. • Each port can be configured in one of the available widths, independent of the other port. The read port width can be different from the write port width for each port. • The memory
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