Berkeley COMPSCI 150 - Sequential Logic Implementation (7 pages)

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Sequential Logic Implementation



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Sequential Logic Implementation

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Lecture Notes


Pages:
7
School:
University of California, Berkeley
Course:
Compsci 150 - Components and Design Techniques for Digital System...
Components and Design Techniques for Digital System... Documents

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Sequential Logic Implementation Abstraction of State Elements Models for representing sequential circuits Divide circuit into combinational logic and state Localize feedback loops and make it easy to break cycles Implementation of storage elements leads to various forms of sequential logic Finite state machines Moore and Mealy Representation of memory states Changes in state transitions Design procedure State diagrams State transition table Next state functions Inputs Outputs Combinational Logic State Inputs State Outputs Storage Elements CS 150 Spring 2007 Lec 6 Moore and Mealy Machines 1 CS 150 Spring 2007 Lec 6 Moore and Mealy Machines 2 Forms of Sequential Logic Finite State Machine Representations Asynchronous sequential logic state changes occur whenever state inputs change elements may be simple wires or delay elements Synchronous sequential logic state changes occur in lock step across all storage elements using a periodic waveform the clock States determined by possible values in sequential storage elements Transitions change of state Clock controls when state can change by controlling storage elements 010 001 In 0 Sequential Logic In 1 100 111 In 0 110 In 1 Sequences through a series of states Based on sequence of values on input signals Clock period defines elements of sequence Clock CS 150 Spring 2007 Lec 6 Moore and Mealy Machines 3 CS 150 Spring 2007 Lec 6 Moore and Mealy Machines 4 Example Finite State Machine Diagram Can Any Sequential System be Represented with a State Diagram Combination lock from first lecture Shift Register ERR closed S1 reset closed mux C1 not new equal new not equal new not equal new S2 S3 closed mux C2 not new equal new closed mux C3 Input value shown on transition arcs Output values shown within state node not equal new not new open 0 0 0 001 CS 150 Spring 2007 Lec 6 Moore and Mealy Machines 5 OUT3 D Q 110 101 0 0 1 1 1 010 1 000 D Q 1 0 1 D Q IN OUT2 CLK 100 OPEN equal new OUT1 111 0 1 0 011 CS 150 Spring 2007 Lec 6 Moore



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