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Berkeley COMPSCI 150 - Finite State Machine on Xilinx

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ImplementationHardware Debugger1 Objective2 Prelab3 Add the Xilinx Interface Circuits4 Preparing your Schematic to be downloaded to hardware5 Download and Test the Circuit6 CheckoffsUniversity of California at BerkeleyCollege of EngineeringDepartment of Electrical Engineering and Computer Sciences CS 150, Fall 2000 J. Wawrzynek, N. Weaver Modified by R. Fearing, D. Young, and N. AboobakerXilinx F1.5 Version: T. SmilksteinLab 3Finite State Machine on Xilinx1 Objective Put your combination lock from Lab 2 onto a chip. To do this, you will: 1. Use Xilinx Flow Engine to compile and route your design.2. Use Xilinx Hardware Debugger to do real-time hardware debugging and watch internal signals1.1 Overview Figure 1. Steps taken in this lab to compile, download, and test designFor a design to be useful, it must make its way into hardware. To do this we will be using Xilinx Field Programmable Gate Arrays (FPGAs), chips that can be configured as many different circuits. Specifically, we will be using the Xilinx XC4000 Design Demonstration Board, which contains an XC4005E FPGA, switches, and light-emitting diodes. These boards are very expensive and not easily replaced. Be very careful with these. Make sure that theystay on the anti-static mat. Make sure also that the ground plug is plugged in. Before touching the Xilinx board, ground yourself-- touch any metal you can find or the static mat. Do not take the Xilinx boards or anything else from 204B Cory! Schematic Editor(Create Netlist, Integrity Test, and Export Netlist)Implementation(Compiling and Routing Design)HardwareDebugger(Downloading to Chip+ Debugging)2 Prelab 1. Answer the questions on the checkoff sheet.2. Make sure your Lab 2 design works and the labels in your schematic match the labels shown in the example.3. Also check that none of your filenames are longer than 8 characters. We're using new software so this might or might not be a problem (it's better to be safe though).4. Make sure your schematic does not use any components from the built-in library. If you followed the instructions in Lab 2, this should not be a problem.5. Make sure none of your symbols or components have the same name as components in the (xc4005e) library, such as DFF or CLB. If you did, rename your components.2.1 Xilinx Interface To compile your design for the Xilinx, some interface components need to be added. We have done the busy work for you. (See section 3.1 below) 2.1.1 I/O Pads I/O pads and buffers are special cells in the (xc4005e) library, and connect the Xilinx to the outside world of buttons, LEDs, and other chips: IPAD Input PadOPAD Output PadIBUF Input BufferOBUF Output BufferEach IPAD and OPAD is connected to a particular pin on the Xilinx, designated by the LOC attribute. For example, in our schematic, the IPAD in the upper-left corner, SW5-1, has the attribute LOC=P27, indicating it connects to pin 27 of the Xilinx. 2.1.2 Debounce Your lock expects ENTER and RESET to be high for exactly one clock cycle every time it is pressed. The DEBOUNCE circuit, a simple state machine, ensures this. 3 Add the Xilinx Interface Circuits We have entered the required interface circuits; you need to copy them into your design. You need to open the TA-provided design and save it as the second sheet in your combination lock schematic. As with one-sheet schematics, nets with the same label on different sheets of the same schematic are connected implicitly. 1. The TA macro library must be added to your library list to make access to some of the symbols possible. Select File  Project Libraries… (or ctrl + L), then, if a library called lab3file is in the list on the left, select it and click on “Add >>”. If it isn’t in the list, click on “Lib Manager…”. Select Library  Attach…, and go to U:\cs150\lab3file\lib. A library called lab3file should appear in the right list window. Press OK. The Project Libraries window should come back up with the library youjust added in the list window on the left. Click on the new library, then click on “Add>>” to add it to your project libraries. As a check, make sure it has shown up in your project manager file list.2. Use File  Open to open U:\cs150\lab3file\lab32.SCH. Then save it under the name lab32.SCH to your own directory using File  Save as…. (Remember to add to project if “Non-project” is displayed in title bar of schematic).3. From the schematic editor, run Options  Create netlist, Options  Integrity test, and Options  export netlist.4 Preparing your Schematic to be downloaded to hardware The next step after successfully exporting your netlist is preparing it for downloading to the chip.The Xilinx Flow Engine, which is started by clicking on the Implementation box (located under the Design Entry box), will compile and route the exported (EDIF) netlist into a bit file that can be downloaded to the Xilinx chip. In the dialog box that comes up after clicking on Implementation, set the Device to 4005EPC84, and Speed to 1. Then run. A new window will pop up showing the progress of the compilation and routing.To look at the results of a compilation, click on the “Versions” tab in your project manager, right click on the revision that you need information on, and select “View Implementation Log” or “Invoke Interactive Flow Engine”. Both will show you a log of the compilation. You can also access the log by clicking on the “Reports” tab and double clicking on “Implementation Log File”. Look through the log and see what information it gives you.There is a tool that let you see graphically the resulting mapping of the logic in the Xilinx chip. Select Tools  Implementation  EPIC Design Viewer/Editor. You should take a look, since it's pretty neat to see. By selecting nets in the EPIC list, you can see how the compiler has routed your wires.5 Download and Test the Circuit 5.1 Connect the power cables and XChecker cables There should be power supplies at all of the stations. The power supplies have a cable with two plugs, red and black. The black is ground, and the red is +5V. 1. Plug in the power supply.2. Ground yourself.3. Connect power to the board. Match black plug to black, red to red.4. The decimal point on CR3 (the left seven-segment LED) should light, indicating the power is


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Berkeley COMPSCI 150 - Finite State Machine on Xilinx

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