Spring 2003 EECS150 – Lec20-fsm2Page 1EECS150 - Digital DesignLecture 20 - Finite State Machines 2April 3, 2003John WawrzynekSpring 2003 EECS150 – Lec20-fsm2Page 2Outline• Moore versus Mealy style state machines.• FSM optimization– State Reduction– State AssignmentSpring 2003 EECS150 – Lec20-fsm2Page 3Finite State Machines• Example: Edge DetectorBit are received one at a time (one per cycle), such as: 000111010 timeDesign a circuit that assertsits output for one cycle when the input bit stream changesfrom 0 to 1. Try two different solutions.FSMCLKINOUTSpring 2003 EECS150 – Lec20-fsm2Page 4State Transition Diagram Solution AZEROOUT=0CHANGEOUT=1ONEOUT=0IN=1IN=1IN=1IN=0IN=0IN=0IN PS NS OUT0 00 00 01 00 01 00 01 00 11 01 11 10 11 00 01 11 11 0ZEROCHANGEONESpring 2003 EECS150 – Lec20-fsm2Page 5Solution A, circuit derivationFFFFOUTINNS1NS0PS1PS0IN PS NS OUT0 00 00 01 00 01 00 01 00 11 01 11 10 11 00 01 11 11 0ZEROCHANGEONE 00 01 11 100 0 0 0 -1 0 1 1 -PSIN 00 01 11 100 0 0 0 -1 1 1 1 -PSIN 00 01 11 100 0 1 0 -1 0 1 0 -PSINNS1= IN PS0NS0= INOUT= PS1 PS0Spring 2003 EECS150 – Lec20-fsm2Page 6Solution BOutput depends non only on PS but also on input, INZEROONEIN=0OUT=0IN=1OUT=1IN=0OUT=0IN=1OUT=0FFOUTNSPSININ PS NS OUT0 0 0 00 1 0 01 0 1 11 1 1 0Let ZERO=0,ONE=1NS = IN, OUT = IN PS’What’s the intuition about this solution?Spring 2003 EECS150 – Lec20-fsm2Page 7Edge detector timing diagramsOUT (solution A)INOUT (solution B)CLK• Solution A: output follows the clock• Solution B: output changes with input rising edge and is asynchronous wrt the clock.Spring 2003 EECS150 – Lec20-fsm2Page 8FSM ComparisonSolution AMoore Machine• output function only of PS• maybe morestates• synchronous outputs– no glitches– one cycle “delay”– full cycle of stable outputSolution BMealy Machine• output function of both PS & input• maybe fewer states• asynchronous outputs– if input glitches, so does output– output immediately available– output may not be stable long enough to be useful (below):CLKINOUTCLCLKOUTIf output of Mealy FSM goes through combinational logic before being registered, the CL might delay the signal and it could be missed by the clock edge.Spring 2003 EECS150 – Lec20-fsm2Page 9FSM RecapMoore Machine Mealy MachineSTATE[output values]input valueSTATEinput value/output valuesBoth machine types allow one-hot implementations.Spring 2003 EECS150 – Lec20-fsm2Page 10FSM Optimization• State Reduction:Motivation:lower cost• fewer flip-flops in one-hot implementations• possibly fewer flip-flops in encoded implementations• more don’t cares in NS logic• fewer gates in NS logicSimpler to design with extra states then reduce later.• Example: Odd parity checker.Two machines - identical behavior.S0[0]S1[1]S2[0]011100S0[0]S1[1]0101Spring 2003 EECS150 – Lec20-fsm2Page 11State Reduction• State Reduction is based on:Two states are equivalent if, for each member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state.If two states are equivalent, one can be eliminated without effecting the behavior of the FSM.• Several algorithms exist:– Row matching method.– Implication table method.• “Row Matching” is based on the state-transition table:If two states have the same output, and both transition to the same next state, or both transition to each other, or both self-loop, then they are equivalent.Combine the equivalent states into a new renamed state.Repeat until no more states are combined.– Note: This algorithm is slightly different than the book.Spring 2003 EECS150 – Lec20-fsm2Page 12Row Matching ExampleNS outputPS x=0 x=1 x=0 x=1a a b 0 0b c d 0 0c a d 0 0d e f 0 1e a f 0 1f g f 0 1g a f 0 1State Transition TableSpring 2003 EECS150 – Lec20-fsm2Page 13Row Matching ExampleNS outputPS x=0 x=1 x=0 x=1a a b 0 0b c d 0 0c a d 0 0d e f 0 1e a f 0 1f e f 0 1NS outputPS x=0 x=1 x=0 x=1a a b 0 0b c d 0 0c a d 0 0d e d 0 1e a d 0 1Reduced State Transition DiagramSpring 2003 EECS150 – Lec20-fsm2Page 14State Reduction• The “row matching” method is not guaranteed to result in the optimal solution in all cases, because it only looks at pairs of states.• For example:• Another (more complicated) method guarantees the optimal solution:• “Implication table” method:See Mano, chapter 9.S0S1S20/11/01/01/00/10/1Spring 2003 EECS150 – Lec20-fsm2Page 15State Assignment (from Katz)• In encoded (non-one-hot) FSMs, the choice of binary encodings for the states has an influence on the number of logic gates (or LUTs) needed to compute the next state and outputs.• For n states, at least s bits are needed for a binary encoding. Where• different encodings exist.• We will look at several “by-hand” heuristic methods for choosing good assignments.• Some CAD tools will make assignments automatically. ns2log=!2sSpring 2003 EECS150 – Lec20-fsm2Page 16State MapsS0S2S3S1S4 00 01 11 100 S0 S4 S31 S1 S2q1 q0q2 00 01 11 100 S0 S1 S3 S21 S4q1 q0q2AssignmentState q2 q1 q0S0 0 0 0S1 1 0 1S2 1 1 1S3 0 1 0S4 0 1 1AssignmentState q2 q1 q0S0 0 0 0S1 0 0 1S2 0 1 0S3 0 1 1S4 1 1 1• “K-maps” are used to help visualize good encodings.• Adjacent states in the STD should be made adjacent in the map.Spring 2003 EECS150 – Lec20-fsm2Page 17State AssignmentAlternative heuristics based on input and output behavior as wellas transitions:Adjacent assignments to:states that share a common next state(group 1's in next state map)states that share a common ancestor state(group 1's in next state map)states that have common output behavior(group 1's in output map)Highest PriorityMedium
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