Verilog Synthesis & FSMsTodayDesigning Digital Logic (1)Designing Digital Logic (2)Designing Digital Logic (3)Designing Digital Logic (4)Efficient Hardware Design (1)Efficient Hardware Design (2)HDL Simulation (1)HDL Simulation (2)Blocking vs. Non-Blocking (1)Blocking vs. Non-Blocking (2)Administrative InfoAdministrative Info (2)Lab #3: The Combo Lock (1)Lab #3: The Combo Lock (2)Lab #3: The Combo Lock (3)Lab #3: The Combo Lock (4)Lab #3: The Combo Lock (5)Lab #3: The Combo Lock (6)Lab #3: The Combo Lock (7)FSMs in Verilog (1)FSMs in Verilog (2)FSMs in Verilog (3)FSMs in Verilog (4)FSMs in Verilog (5)01/13/19 EECS150 Lab Lecture #3 1Verilog Synthesis & FSMsEECS150 Spring 2008 – Lab Lecture #3Shah Bawany01/13/19 EECS150 Lab Lecture #3 2TodayDesigning Digital LogicEfficient Hardware DesignHDL SimulationBlocking vs. Non-BlockingAdministrative InfoLab #3: The Combo LockFSMs in Verilog01/13/19 EECS150 Lab Lecture #3 3Designing Digital Logic (1)High Level DesignTop-Down DesignBreak down a larger module (ie combo lock) into smaller more manageable partsImplementing the DesignFollow the flow of dataPort specifications for modules provided in lab documentSimple FSMGet inputsUpdate stateGenerate outputs01/13/19 EECS150 Lab Lecture #3 4Designing Digital Logic (2)Start with InputsWhat are they?In this case values from the dipswitches as well as reset, reset combo and enterThey’ll often be outputs from other modulesProcess ThemRaw inputs are often not what you needi.e. Lab3, current combination is stored in registers, so we can process the inputs using a comparator before handing it off to the FSM01/13/19 EECS150 Lab Lecture #3 5Designing Digital Logic (3)Determine StateWhat does the module need to remember?Common tasks are determining if it seen a particular input or counting how many cycles have passed since an eventIn this lab, our FSM only knows of correct versus incorrect entries, as we have abstracted away knowledge of specific inputsDesign Memory for StateGeneralized FSM - Mutli-purpose using 2 always @ blocksCounter - Generally good for timing eventsShift Register - Serial <--> Parallel01/13/19 EECS150 Lab Lecture #3 6Designing Digital Logic (4)Generate OutputsWhat are they?Values passed outside the moduleCreate the outputsDon’t set them, they’re not variablesCompute them from state (and inputs)Learn to think in Boolean equationsassign is helpful01/13/19 EECS150 Lab Lecture #3 7Efficient Hardware Design (1)CaB1A01ZaA01auxZBCalways @ (*) beginif (a) aux =B;else aux = C;Z = A + aux;endORassign Z = A + (a ? B : C);always @ (*) beginif (a) Z = A + B;else Z = A + C;end01/13/19 EECS150 Lab Lecture #3 8Efficient Hardware Design (2)BZA<<AZn+1 bit adderassign B = 3;assign Z = A * B;Multipliers are bad for synthesisassign Z = A + (2 * A);assign Z = A + (A << 1);assign Z = A + {A, 1’b0};01/13/19 EECS150 Lab Lecture #3 9HDL Simulation (1)Software Based SimulationFast, simple and mostly accurateAllows for simulation at any precisionEasy to see any signal - perfect VisibilityDrawbacksSimulator DependantTime to simulate a single clock cycle is much slower than the actual clock speed, so extensive testing may take longerSimulation != Synthesis01/13/19 EECS150 Lab Lecture #3 10HDL Simulation (2)ImplicationsSome blocks of Verilog are not executedThings don’t necessarily happen in orderVerilog is SIMULATEDNeed to specify test input vectors, which can be painful01/13/19 EECS150 Lab Lecture #3 11Blocking vs. Non-Blocking (1)always @ (a) beginb = a;c = b;endalways @ (posedge Clock) beginb <= a;c <= b;endC = B = AB = AC = Old BVerilog Fragment Result01/13/19 EECS150 Lab Lecture #3 12Blocking vs. Non-Blocking (2)Use Non-Blocking for FlipFlop Inferenceposedge/negedge require Non-BlockingElse simulation and synthesis wont matchUse #1 to show causalityalways @ (posedge Clock) beginb <= #1 a;c <= #1 b;end01/13/19 EECS150 Lab Lecture #3 13Administrative InfoDon’t expect to be checked off during any lab times other than your ownYou should get checked off during your lab or during your lab TA’s office hoursIf your another TA does check you off, bring your checkoff sheet to your regular lab TAAt the end of lab, come up and put your 5-digit cardkey access number on the sheet if you didn’t already during lab.01/13/19 EECS150 Lab Lecture #3 14Administrative Info (2)Partners - 1 week warningYou MUST have one for Lab4 and later…Try to keep the same one for the projectThey must be in your lab sectionIf you do not have a partner:Find one now!Post to the newsgroup01/13/19 EECS150 Lab Lecture #3 15Lab #3: The Combo Lock (1)Used to control entry to a locked room2bit, 2 digit combo (By Default 11, 01)Set code to 11, Press EnterSet code to 01, Press EnterLock Opens (Open = 1)Lab4Top(Lab4Lock)0101Lab4CompareOpenErrorProg1Prog2ResetComboResetEnterCode[0]Code[1]DIPSwitchesButtonsOutputsYour Verilog01/13/19 EECS150 Lab Lecture #3 16Lab #3: The Combo Lock (2)Signal Width Dir DescriptionCode2 I Code from the dipswitchesEnter1 I Enter button (examine the code)ResetCombo1 I Reset to the default combinationClock1 I System ClockReset1 I System Reset, doesn’t affect the comboOpen1 O Indicates the lock is openError1 O Indicates a bad combinationProg11 O Reprogramming the first digitProg21 O Reprogramming the second digitLED8 O Use these for debugging01/13/19 EECS150 Lab Lecture #3 17Lab #3: The Combo Lock (3)Example 1:1: Press ResetCombo, Combo: 2’b11, 2’b012: Set 2’b11, Press Enter3: Set 2’b01, Press Enter, LEDs: “OPEN”4: Press Enter, LEDs: “Prog1”5: Set 2’b00, Press Enter, LEDs: “Prog2”6: Set 2’b10, Press Enter, LEDs: “OPEN”7: Combo: 2’b00, 2’b1001/13/19 EECS150 Lab Lecture #3 18Lab #3: The Combo Lock (4)Example 2:1: Press ResetCombo, Combo: 2’b11, 2’b012: Set 2’b01, Press Enter3: Set 2’b01, Press Enter, LEDs: “Error”Why doesn’t “Error” show until step 3?01/13/19 EECS150 Lab Lecture #3 19Lab #3: The Combo Lock (5)InitOK1 BAD1OK2[Open]Prog1[Prog1]Prog 2[Prog2]BAD2[Error]Code 1 &Enter~Code1 &EnterCode 2 & EnterEnterEnterEnter~Code2 &EnterEnter01/13/19 EECS150 Lab Lecture #3 20Lab #3: The Combo Lock (6)C ode 1R eg==C ode 2R eg==Lab4CompareD ecode 2D ecode 1C odeEnterProg1/Prog2In itOK 1 BAD 1OK 2[Op e n ]Pro g 1[Pro g 1 ]Pro g
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