Spring 2010EECS150 - Lec8-cmosPage EECS150 - Digital DesignLecture 8 - CMOS Implementation TechnologiesFeb 11, 2010John Wawrzynek1Spring 2010EECS150 - Lec8-cmosPage Mux4 Testbench2module testmux4; reg [5:0] count = 6’b000000; reg a, b, c, d, expected; reg [1:0] S; wire f; mux4 myMux (.select(S), .in0(a), .in1(b), .in2(c), .in3(d), .out(f)); initial begin repeat(64) begin {S, d, c, b, a} = count[5:0]; case (S) 2’b00: expected = a; 2’b01: expected = b; 2’b10: expected = c; 2’b11: expected = d; endcase // case(S) #8 $strobe( "select=%b in0=%b in1=%b in2=%b in3=%b out=%b, expected=%b time=%d", S, a, b, c, d, f, expected, $time); #2 count = count + 1’b1; end $stop; end endmoduleAlternative to $strobe in this case,#8 if (f != expected) $display(“Mismatch: ...);Wait a bit, then bump count.Declaration and initialization all at once. Generally not available in synthesis.DUT instantiationEnumerate all possible input patterns.Apply pattern to DUTBehavioral model of mux4$strobe displays data at a selected time. That time is just before simulation time is advanced (after all other events).Delay to allow mux outputs to stabilize. Here we assume mux delay < 8ns.Spring 2010EECS150 - Lec8-cmosPage module testFSM; reg in; wire out; reg clk=0, rst; reg expect; FSM1 myFSM (.out(out), .in(in), .clk(clk), .rst(rst)); always #5 clk = ˜clk; initial begin rst=1; #10 in=0; rst=0; expect=0; #10 in=1; rst=0; expect=0; #10 in=0; rst=0; expect=0; #10 in=1; rst=0; expect=0; #10 in=1; rst=0; expect=1; #10 in=1; rst=0; expect=1; #10 in=0; rst=0; expect=0; #10 $stop; end always begin #4 $strobe($time," in=%b, rst=%b, expect=%b out=%b", in, rst, expect, out); #6 ; end endmoduleFSM Testbench Example3DUT instantiation100MHz clk signalself-loopstart in IDLEtransition to S0transition to IDLEtransition to S0transition to S1self-looptransition to IDLENote: Input changes are forced to occur on negative edge of clock.Strobe output occurs 1ns before rising edge of clock.FSM Verification/Debug is easier if you have access to state value also. Either 1) bring out to ports, or 2) use waveform viewer.Test all arcs.Spring 2010EECS150 - Lec8-cmosPage Final Words (for now) on SimulationTesting is not always fun, but you should view it as part of the design process. Untested potentially buggy designs are a dime-a-dozen. Verified designs more rare and have real value.Devising a test strategy is an integral part of the the design process. It shows that you have your head around the design. It should not be an afterthought.4Spring 2010EECS150 - Lec8-cmosPage Overview of Physical Implementations• Integrated Circuits (ICs)– Combinational logic circuits, memory elements, analog interfaces. • Printed Circuits (PC) boards– substrate for ICs and interconnection, distribution of CLK, Vdd, and GND signals, heat dissipation. • Power Supplies– Converts line AC voltage to regulated DC low voltage levels. • Chassis (rack, card case, ...) – holds boards, power supply, fans, provides physical interface to user or other systems. • Connectors and Cables. The stuff out of which we make systems.5Spring 2010EECS150 - Lec8-cmosPage Printed Circuit Boards• fiberglass or ceramic• 1-25 conductive layers • 1-20in on a side • IC packages are soldered down.Multichip Modules (MCMs)• Multiple chips directly connected to a substrate. (silicon, ceramic, plastic, fiberglass) without chip packages.6Spring 2010EECS150 - Lec8-cmosPage Integrated Circuits• Primarily Crystalline Silicon• 1mm - 25mm on a side• 100 - 1000M transistors• (25 - 250M “logic gates")• 3 - 10 conductive layers• 2010 - feature size ~ 45nm = 0.045 x 10-6 m • “CMOS” most common - complementary metal oxide semiconductor• Package provides:– spreading of chip-level signal paths to board-level – heat dissipation. • Ceramic or plastic with gold wires. Chip in Package7Spring 2010EECS150 - Lec8-cmosPage Integrated Circuits• Moore’s Law has fueled innovation for the last 3 decades.• “Number of transistors on a die doubles every 18 months.”• What are the consequences of Moore’s law?8Spring 2010EECS150 - Lec8-cmosPage 9Chip-level Function Implementation AlternativesFull-custom: All circuits/transistor layouts optimized for application.Standard-cell: Arrays of small function blocks (gates, FFs) automatically placed and routed.Gate-array/structured-ASIC: Partially prefabricated wafers customized with metal layers.FPGA: Prefabricated chips customized with switches and wires.GPP (general purpose processor): fixed architecture customized through software. Domain Specific Processor: (Digital Signal Processor, Network Processor, Graphics Processing Unit).What are the important metrics of comparison?ASICSpring 2010EECS150 - Lec8-cmosPage 10Why FPGAs?FPGAASICA tradeoff exists between NRE* cost and manufacturing costs:The ASIC approach is only viable for products with very high volume (where NRE could be amortized), and which were not time to market (TTM) sensitive.Cross-over point has moved to the right (favoring FPGA) implementation as ASIC NREs have increased.*Non-recurring Engineering CostsSpring 2010EECS150 - Lec8-cmosPage CMOS DevicesCross SectionTop View• MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The gate acts like a capacitor. A high voltage on the gate attracts charge into the channel. If a voltage exists between the source and drain a current will flow. In its simplest approximation, the device acts like a switch. nFETpFET11Spring 2010EECS150 - Lec8-cmosPage Transistor-level Logic Circuits12Inverter (NOT gate):NAND gate:How about AND gate?Note:• out = 0 iff a AND b =1 therefore out = (ab)’• pFET network and nFET networks are duals of one another.For example, consider the NAND gate:Spring 2010EECS150 - Lec8-cmosPage Transistor-level Logic CircuitsnFET is used only to pass logic zero.pFET is used only to pass logic one.Simple rule for wiring up MOSFETs: Note: This rule is sometimes violated by
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