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Berkeley COMPSCI 150 - Synchronous

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Synchronous {Pipelines, dataflow}Honors Discussion #4EECS 150 Spring 2010Chris W. Fletcher1UCB EECS150 Spring 2010, Honors #4Today• SCORE commentary• Synchronous pipelines• Throughput case study2UCB EECS150 Spring 2010, Honors #4Big Picture• This week: Synchronous pipelines & data transactions• Next week: Asynchronous pipelines& data transactions• After that: … putting it all together…{Synchronous, Asynchronous} FIFOs3UCB EECS150 Spring 2010, Honors #4Synchronous Pipelines 1• Where do we start?With the simple case…This circuit is called a shift register or (de)serializer• If you put logic in between each stage…You get a pipeline!4Synchronous Pipelines 2• When/how does this work?– System puts data into the pipeline… knowing that it will come out at a known time– Considerations• Must know each module’s “latency” (doesn’t have to == 1)• Make sure the output is ready by the time it sees the data!1 2 3 4 5 6 7 85UCB EECS150 Spring 2010, Honors #4Synchronous Pipelines 3• What happens when you want to stop?(i.e. output isn’t ready when the data arrives)ReadyTrain wreck!How do we fix this?Add control logic6Synchronous Pipelines 4• Monolithic/lock-step approach:1. Controller-timed• Controller keeps time• Handles 1/2+ cycle stages1. Self-timed• Each module keeps time• Handles 1/2+ cycle stagesControlEnable Enable Enable EnableReady ControlReadyEnable Enable Enable EnableDone Done Done Done7Synchronous Pipelines 5• Monolithic/lock-step pitfall– Each can handle multi-stage operations– But what does this do to performance?– Well, NO data moves in any stage…until the slowest stage is done.– Consider (try to find the bottleneck assuming lock-step):8Synchronous Pipelines 6• “Decoupled” approach– No central controller– Latency Insensitive– Each module keeps track of its own time– Data moves at the rate of each modulenot the rate of the slowest piece– Sound familiar?ValidReady9UCB EECS150 Spring 2010, Honors #4Throughput Considerations 1• A look under the covers– What is this register?{E,R,S} match the Virtex-5– What events can occur?FFD QSRInValidOutValidOutReadyInReady1'bxE1'b0FFD QEInDataReadWriteWrite Read0 0Action0 11 01 1No changeClearSet???What are the implications of this state being unreachable?10Throughput Considerations 2• What we want: full throughput when…Sender is constantly sending (InValid = 1 always)Receiver is constantly receiving (OutReady = 1 always)11ValidReady1'b11'b1Write Read0 0Action0 11 01 1No changeClearSet???But can we ever get ideal throughput?InValidInReadyOutValidOutReadyClockHomework• Thought problem– Fix the throughput issue (allow for ideal throughput)• (More) reading will be postedUCB EECS150 Spring 2010, Honors #4 12Acknowledgements & ContributorsSlides developed by Chris Fletcher (2/2010).This work is based in part on slides by:Krste Asanovic, John Wawrzynek, and John LazzaroAnd is based on ideas by:Greg GibelingThis work has been used by the following courses:– UC Berkeley CS150 (Spring 2010): Components and Design Techniques for Digital Systems 13UCB EECS150 Spring 2010, Honors


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Berkeley COMPSCI 150 - Synchronous

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