Time TableEECS150: Homework 13, RTL, Scheduling, and RegistersUC Berkeley College of EngineeringDepartment of Electrical Engineering and Computer Science1 Time TableASSIGNED Friday, April 24thDUE Friday, May 1stat 2pmHomework submission will only be through SVN. Email submissions will not be ac-cepted!1. Consider the design of a simple processor used to add the contents of blocks of 4 bytes in consecutivememory locations. The datapath circuit for the processor is shown in Figure 1.Figure 1 Datapath for the processor used to add the contents of blocks of 4 bytes in consecutive memorylocations.The processor has one data input (8-bit wide) named BASE, an input control signal named ENABLE,and 3 internal control signals - MUX, LD, and RST. The datapath contains three data registers - MAR,MDR, and X. After the processor performs its operation, the Z register is left with the sum of memorylocations BASE, BASE + 1, BASE + 2, and BASE + 3. We assume that a controller (not shown) will1take as input the ENABLE signal and generate MUX, RST, and LD. To begin the addition operation, anexternal circuit asserts ENABLE for 1 clock cycle then lowers it for a minimum of 12 cycles.Write the RTL level description for the sequence of transwers that must occur after the ENABLEsignal is asserted. Try to minimize the total number of cyc les.2. Imagine a datapath that has four computation units; two adders, a multiplier, and a shifter. Eachunit requires an entire clock cycle (minus flip-flop overheads) to complete its operation and isfollowed by a register to hold its output. The graph in Figure 2 represents an iterative operationto be completed on the datapath. Each node is labeled with the name of the computation unitthat it requires plus a unique letter identifying the node. Note that there is no feedback (or loopcarry dependence) in this computation.Figure 2 Graph of the operations needed for each iteration.Use modulo scheduling to show how to complete four iterations of the loop in the minimum numberof cycles. Show your work then fill in the chart in Figure 3 the unique integer node numbers fromthe graph. Use subscripts (1, 2, 3, and 4) to indicate the iteration number. For instance, ”C2”indicates node C of iteration 2.3. Modify the D-type flip-flop given in Figure 4 to add a synchronous Reset and a synchronousSet.4. Modify the D-type flip-flop given in Figure 4 to add an asynchronous Clear and an asynchronousPreset.5. Building flip-flops out of other kinds of flip-flops.(a) Sketch a circuit for a D-type flip-flop based on a JK-type flip-flop.(b) Sketch a circuit for a JK-type flip-flop based on a D-type flip-flop.(c) Sketch a circuit for a T-type flip-flop based on a D-type flip-flop.6. Draw the circuit for a 5-bit LFSR with the following primitive polynomial: X5+ X2+ 1.2Figure 3 Fill this in with how you would schedule the operations needed to complete 4 iterations.Figure 4 A D-type flip-flop implemented using cross-coupled NAND
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