IntroductionMotivationA Basic FSMThe FSM in Verilog1: Creating a State Encoding2: Keeping Track of the Current State!wire! and !reg! Elements in VerilogConventions[language=Verilog]!wire! Elements (Combinational logic)[language=Verilog]!reg! Elements (Combinational and Sequential logic)When [language=Verilog]!wire! and [language=Verilog]!reg! Elements are Interchangable3: Transitioning from State to State!always@! Blocks in Verilog[language=Verilog]!always@! Blocks[language=Verilog]!<=! (non-blocking) Assignments[language=Verilog]!=! (blocking) Assignments[language=Verilog]!always@(posedge Clock)! Blocks[language=Verilog]!always@( * )! BlocksPitfallsPost-!always@!: Specifying our FSM's Transition Behavior4: Outputting Values Based on the !CurrentState!A Complete FSMEECS150: Finite State Machines in VerilogUC Berkeley College of EngineeringDepartment of Electrical Engineering and Computer Science1 IntroductionThis document describ e s how to write a finite state machine (FSM) in Verilog. Specifically, in EECS150,you will be designing Moore machines for your project. This document only discusses how to describeMoore machines.Moore machines are very useful because their output signals are synchronized with the clo ck. Nomatter when input signals reach the Moore Machine, its output signals will not change until the risingedge of the next clock cycle. This is very important to avoid setup timing violations. For example, ifa Mealy machine’s input signal(s) changes sometime in the middle of a clock cycle, one or more of itsoutputs and next state signals may change some time later. “Some time later” might come after thesetup time threshold for the next rising edge. If this happens, the registers that will hold the FSMs nextstate may receive garbage, or just incorrect inputs. Obviously, this amounts to a bug(s) in your FSM. Avery painful and difficult-to-find bug at that.The tradeoff in using the Moore machine is that sometimes the Moore machine will require morestates to specify its function than the Mealy machine. This is because in a Moore machine, outputsignals are only depe ndent on the current state. In a Mealy machine, outputs are dependent on boththe current state and the inputs. The Mealy machine allows you to specify different output behavior fora single state. In EECS150, however, the FSMs that you will be designing do not typically have enoughstates for this to create a significant problem. We will err on the side of caution, and vie for a safe butsometimes more verbose FSM implementation, in this course.2 MotivationEECS150 is concerned with circuit design. You will be using Verilog to describe your circuits. Unfor-tunately, Verilog, being originally designed to support circuit simulation rather than circuit synthesis, ischalked full of syntactical idiosyncrasies that, if not prop e rly understood, will create odd bugs in yourdesigns. This document will show you how to write a Moore FSM in a template-based fashion. This“cookie-cutter” approach is designed to avoid Verilog’s bug-prone areas, while keeping your code as non-verbose as possible. Verilog is a means to an end. This document will show you how to get to the point:designing circuits; while fighting Verilog as little as possible.3 A Basic FSMFigure 1 depicts an example Moore FSM. You can tell that this is a Moore machine because the outputsare shown inside [. . .]s instead of on state transition arcs. The following sections will refer to Figure 1 asan example use-case for the Moore machine FSM template.The FSM shown in Figure1 is useful because it exemplifies the following:1. The concept of an initial state.12. States with non-conditional outward transitions.3. States with conditional outward transitions.1There must always be an initial state for the FSM to start at after a Reset.1Figure 1 A basic FSM!(A & B)!((!A & B) | (A & !B))A & !B!A & BA!AA & BResetSTATE_1[Output1]STATE_2[Output1, Output2,Status = 3'b010]STATE_3[Status = 3'b011]STATE_InitialSTATE_4& logical and| logical or! logical not4. States that loop back onto thems elves.5. States with no outward transitions.We would like to be able to express this type of behavior in a Verilog-written FSM.4 The FSM in VerilogIn looking at Figure 1, we will need a way to express the following in Verilog:1. A state encoding for each s tate.2. A mechanism for keeping track of the current state.3. Transitions from state to state.4. Output values based on the current state.We will construct the FSM one step at a time.4.1 1: Creating a State EncodingWe will create our state encoding with Verilog parameters. Parameters are symbolic constants witheither global (given by the Verilog keyword parameter) or module (localparam) scope. Because we onlywant our state encoding to be visible to the module in which we will write the FSM, we will use thelatter: localparam. With this in mind, we can specify Program 1.2Program 1 The state encoding (in decimal)1 localparam STA TE _Init ia l = 3’ d0 ,2 STA TE_1 = 3’ d1 ,3 STA TE_2 = 3’ d2 ,4 STA TE_3 = 3’ d3 ,5 STA TE_4 = 3’ d4 ;In Program 1, the 3’d notation indicates that the number specified is in the decimal radix. If we wereto use 3’b, the encoding would look like that shown in Program 2. Both implementations are equivelent.Base 10, or 3’d, is typically easier to read.Because this FSM has 5 total s tates, we must allocate 3 bits to specify the encoding (hence 3’das opp ose d to 2’d or 4’d. This is extremely important. If you specify too few bits for your stateencoding, Verilog will not warn you. In fact, when synthesized, each state will only get as many bits asyou provide. For example, if STATE_4 was sp e cified like this: STATE_4 = 2’d4, STATE_4 would be specifiedas 00, the bottem 2 bits of what was intended, namely 100.Program 2 The state encoding (in binary)1 localparam STA TE _Init ia l = 3’ b000 ,2 STA TE_1 = 3’ b001 ,3 STA TE_2 = 3’ b010 ,4 STA TE_3 = 3’ b011 ,5 STA TE_4 = 3’ b100 ;As 3 bits can specify a total of 8 states (0-7), our encoding specifies 3 potential states not specifiedas being actual states. There are several ways of dealing with this problem:1. Ignore it, and always press Reset as a way of initializing the FSM.2. Specify these states, and make non-conditional transitions from them to the STATE_Initial.To reduce ambiguity, we will choose the second option, which makes our final state encoding thatshown in Program3.Program 3 The state encoding with place-holder states (in
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