CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 1Understanding Engineers #1! The graduate with a Science degree asks, "Why doesit work?"! The graduate with an Engineering degree asks, "Howdoes it work?"! The graduate with an Accounting degree asks, "Howmuch will it cost?"! The graduate with an Arts degree asks, "Do you wantfries with that?"CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 2Understanding Engineers #2! MS CS -- Soft-ware! MS EE -- Hard-ware! MBA -- Un-a-ware! MFA -- No-wareCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 3Midterm II! THIS Thursday, 22 March (that is TWO days from today!),2:10 -- 3:30+, CS 150 Lab! Lectures 10, 11, 12, (no lecture 13!), 14, 15, 16;Labs #4 and #5 (Debugging/Logic Analyzers) + Checkpoints #0and #1 (SDRAM + Video Encoder)! Don’t forget: Spring 05/Fall 05 exams are on-line!! 5 x 10 point questions, mostly design-oriented! Closed book, open crib sheet; PENCIL, not pen!! Two review sessions: Tu 8 PM and W 8 PM in the lab! NOTE: Discussion sections and lab lecture cancelled this weekCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 4Sequential Logic Implementation! Models for representing sequential circuits"Mealy, Moore, and synchronous Mealy machines"Verilog specifications for state machines! Finite state machine design procedure"Deriving state diagram from word specifications"Deriving state transition table"Determining next state and output functions"Implementing combinational logicCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 5SDRAM Memory Controller! Static RAM Technology" 6T Memory Cell" Memory Access Timing! Dynamic RAM Technology" 1T Memory Cell" Memory Access Timing! Theory in lecture, but practical detailed memorysystem organization and timing in Lab Checkpoint #0CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 6Two-way Video Conferencing Project! Project Concept and Background! SDRAM Controller (Checkpoint #0)! Video Encoder/Display System (Checkpoint #1)CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 7Videoconferencing System ConceptDisplayVideo EncoderVideo Encoder(Checkpoint #1)Video DecoderCameraVideostreamVideoDecoderCheckpoint #2Checkpoint #4SDRAM(Checkpoint #0)Multiport SDRAMMemory SystemMultiportArbitrationWireless Transceiver(Checkpoint #3)CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 8Computer Organization! Computer design as an application of digital logic design procedures! Computer = processing unit + memory system! Processing unit = control + datapath! Control = finite state machine" Inputs = machine instruction, datapath conditions" Outputs = register transfer control signals, ALU operation codes" Instruction interpretation = instruction fetch, decode, execute! Datapath = functional units + registers" Functional units = ALU, multipliers, dividers, etc." Registers = program counter, shifters, storage registersCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 9Register TransferLdCASel0BSel1DECSel01C ! A Sel ! 0; Ld ! 1C ! B Sel ! 1; Ld ! 1ClkSelLdClkA on BusLd Cfrom BusBusB on Bus?CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 10Register Transfer! Point-to-point connection" Dedicated wires" Muxes on inputs ofeach register! Common input from multiplexer" Load enablesfor each register" Control signalsfor multiplexer! Common bus with output enables" Output enables and loadenables for each registerrtMUXrsMUXrdMUXR4MUXrsMUXrt rd R4BUSrs rt rd R4CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 11State Machine Implementation! Alternative controller FSM implementationapproaches based on:" Classical Moore and Mealy machines" Time state: Divide and Counter" Jump counters"Microprogramming (ROM) based approaches#branch sequencers#horizontal microcode#vertical microcodeCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 12Time State (Divide & Conquer)Time State FSMMost instructions follow same basic sequenceDiffer only in detailed execution sequenceTime State FSM can be parameterized by opcode and AC statesInstruction State:stored in IR<15:14>Condition State:stored in AC<15>T0T1T2T3T4T5T6T7Wait/Wait/Wait/Wait/Wait/Wait/BRN • AC ! 0/(LD + ST + ADD) • Wait/BRN + (ST • Wait)/(LD + ADD) • WaitIR=11=10=01=00LD STADD BRNAC<15>=0AC<15>=1AC ? 0AC < 0"CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 13Jump CountersPure Jump CounterLogic blocks implemented via discrete logic, PLAs, ROMsNOTE: No inputs tojump state logicInputsCount, Load, Clear LogicJump State LogicSynchronous Counter State RegisterClearLoadCountCLOCKCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 14Jump CountersHybrid Jump CounterLoad inputs arefunction of stateand FSM inputsInputsCount, Load, Clear LogicJump State LogicClearLoadCountSynchronous Counter State RegisterCLOCKCS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 15Jump CountersCLR, CNT, LDimplemented via Mux LogicActive Lo outputs:hi input inverted atthe outputNote that CNT isactive hi on counterso invert MUX inputs!CLR = CLRm + ResetCLR = CLRm + Reset/CLR++ +163154150150150/CLRm/Reset/CLRCNTJump StateIR<15>IR14IR15IR<14>3 2 1 0P TCLKD C B ARCOQD QC QB QALOADCLR/LDResetWait/Reset/Wait1 01 0G2 G1D C B AWait/WaitEOUTEOUT EOUT/WaitCNT10/CLRm /LD1514131211109876543210\S13\S12\S11\S10\S9\S8\S7\S6\S5\S4\S3\S2\S1\S0E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1E0GS3 S2 S1 S0E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1E0GS3 S2 S1 S0E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1E0GS3 S2 S1 S0CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 16Branch Sequencers4 Way Branch SequencerCurrent State selects two inputs to form part of ROM addressThese select one of four possible next states (and output sets)Every state has exactly four possible next statesMuxMuxI n p u t s64 Word ROM#$statex11 x10 x01 x00Z Y X WC o n t r o lS i g n a l sa0 a1a2 a3a4a5NW XYZ$ #$ #$ #$ #CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 17Branch SequencersAlternativeHorizontalImplementationInput MUX controlled by encoded signals, not stateMuch fewer inputs than unique states!In example FSM, input MUX can be 2:1!Adding length to ROM word saves on bits vs. doubling wordsVertical format: (14 + 4) x 64 = 1152 ROM bitsHorizontal format: (14 + 4 x 4 + 2) x 16 = 512 ROM bitsM U X! and " MUX ControlDatapath Control Signalsn bit state register4:1 MUXA0 A1 A2 A3! "! "! "! "M U XI N P U T S01!"1 0n-1 1 0n-1 1 0n-1 1 0n-1. . .bit 0bit 1bit n-10 1 2 34:1 MUX0 1 2 3CS 150 - Spring 2007 – Lec #18 – Mid #2 Review - 18Vertical
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