University of California at BerkeleyCollege of EngineeringDepartment of Electrical Engineering and Computer SciencesEECS 150 R. KatzFall 2000 N. ZhouCheckpoint 4Packet Transmission Reception1 ObjectiveFor this checkpoint you will make additions to your UART design fromcheckpoint 2 so that you can transmit and receive packets according to the protocoldefined for this semester’s 150 project.2 Protocol DetailsFor this project we will define a packet as a series of 5 UART transmissions. Thefirst byte of a transmission is called the header, the four remaining bytes will be the dataof the transmission, in this case it will be four samples of audio waveform.In the header byte bits 7,6 are control bits, which are zero for all normal packets.(You may use these bits to extend the protocol to introduce extra features for extra creditin the final project) bits 5,4,3 are the destination of a transmission, and bits 2,1,0 are thesource of the transmission.(See my power point slides for illustration of a packet)The procedure for transmitting a packet is as follows:1. Always listen to what is happening on the shared bus. This means that the RX unitreceives all transmissions on the shared line, including your own transmission.2. Start transmission only after a random waiting period after the bus becomes idle.The bus is considered idle if there as been 16 consecutive ‘1’ at 250KHz orimmediately after a packet transmission.3. If two stations happen to start a transmission at the same time then thetransmission that has the first 0 in the transmission wins. (Notice a transmissionshould never interrupt the middle of another transmission because once the startbit is detected for the first transmission the bus is not idle anymore)4. The winner goes on transmitting as if nothing was wrong.5. The loser notices that a collision has happened, stops transmission immediately,and goes back to step 2 to try again later.3 WiringFor this checkpoint you will receive one chip (DS96176CN Differential LineTransceiver), one discrete package with 3 resistors on it, and a 7ft twisted pair wire forconnecting different stations. The wiring should be done as follows: (you will need toinvert your TX from your UART to get TX.L)DS96176CN FPGADO pin1 RXRE.L pin2 GNDDE pin3 GNDDI pin4 TX.LA(+) and B(-) should be wire-wraped to 2 consecutive pins on the board so that you canplug in the twisted pair wires.Important: because TX.L is wired into the DE the transceiver only actively drives a ‘0’onto the bus. The resistors are used to passively pull the bus to a ‘1’ when nothing isdriving. This means that when the TX from different boards different values, ‘0’ alwayswins. This is very important for figuring out collisions and is also the reason why thetransmission with the first ‘0’ wins the collision.18293 104 11VccB(-)A(+)GNDDORE.LDEDIDS96176CNDifferentialLine Transceiver 2K A(+)0.56K B(-) 2K4 Your design.For this checkpoint you are expected to design an implementation of the packetcommunication protocol described earlier. Your design should transmit one packet eachtime the SPARE button is pushed. The header of the packed should be taken from thedipswitches. The four data bytes can be arbitrarily chosen (for ease of testing you shouldchoose 4 different numbers). There will be a provided bit file for testing your logicdesign. You can use your UART bit file from chkpt2 to test your physical wiring.Specs for the provided bit file:a) The provided bit file will attempt to transmit one packet every 2KHz.b) The header for the packet being transmitted packet is all ‘0’.c) The data packet contains the “secret” message.d) The provided bit file has a zero random wait time, so on a “coin toss” it always wins.e) The provided bit file filters out any packet with destination of ‘000’. (Ignores it’s owntransmissions)f) The spare button chooses which byte from the four data bytes of a received packet todisplay.Specs expected for your design:a) Transmit one packet every time SPARE is pushed. The header of the packet shouldcome from the DIPSWITCH.c) Correctly waits for the bus to be idle and correctly implement pseudo-random waittime before starting transmission. Use (6 bits of a 2MHz 8 bit LFSR) = ([5:0] HeaderByte) as the random start time. d) Correctly implements collision detection and back off.f) Correctly detects the idle state of the bus, 16 ‘1’s, or immediately after a completedpacket. (Note there should never be 16 ‘1’s in the middle of a packet, if it does happenthat means something went wrong and the current packet should be aborted)g) Correctly receives packets from the bus, and latches the data portions of the packetinto display registers after reception of a completed packet. (You do not need to do anyfiltering of the packets for destination check for this checkpoint)b) Switch which byte of received packet to display every time SPARE is pushed.Testing:For testing your design:a) Load your compiled bit file onto one board.b) Load the provided bit file to another board.c) Connect the A(+), B(-) of the 2 boards with the twisted pair wires.d) If all goes well your design should display the “secret” message from theprovided bit file, and the provided bit file will display your transmission.Name_______________________________ Name_______________________________Lab Section (Check one)M: AM T: AM W:AM Th: PM PMPMPMCheckpoint 4 Check-offs• Explain the network protocol to a TATA: ________________ (10%)• Show your schematics to a TA and explain your DATAPATH and how it functions.TA: ________________ (10%)• Show and explain some representation of the FSM you have designed to generate thecontrol signal for your DATAPATH.TA: ________________ (10%)• Verify that your design works by showing that you can receive your own packet.TA: ________________ (10%)• Verify your design with another board loaded with the TA bit file.TA: ________________ (50%)• Use the digital analyzer to show that your design indeed does wait for the bus to beidle before transmission.TA: ________________ (10%)Turned in on timeTA: ________________ (×100%)Turned in 2 week lateTA: ________________
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