CS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 1Sequential Logic! Sequential Circuits" Simple circuits with feedback" Latches" Edge-triggered flip-flops!Timing Methodologies"Cascading flip-flops for proper operation"Clock skew! Basic Registers" Shift registers" CountersCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 2C1 C2 C3comparatorvalueequalmultiplexerresetopen/closednew equalmux controlclockcomb. logicstateSequential Circuits! Circuits with Feedback" Outputs = f(inputs, past inputs, past outputs)" Basis for building "memory" into logic circuits" Door combination lock is an example of a sequential circuit# State is memory# State is an "output" and an "input" to combinational logic# Combination storage elements are also memoryCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 3X1X2•••XnswitchingnetworkZ1Z2•••ZnCircuits with Feedback! How to control feedback?" What stops values from cycling around endlesslyCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 4"remember""load""data""stored value""0""1""stored value"Simplest Circuits with Feedback! Two inverters form a static memory cell" Will hold value as long as it has power applied! How to get a new value into the memory cell?" Selectively break feedback path" Load new value into cellCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 5RSQQ'RSQR'S'QQQ'S'R'Memory with Cross-coupled Gates! Cross-coupled NOR gates" Similar to inverter pair, with capability to force output to 0(reset=1) or 1 (set=1)! Cross-coupled NAND gates" Similar to inverter pair, with capability to force output to 0(reset=0) or 1 (set=0)CS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 6ResetHoldSet SetResetRaceRSQ\Q100Timing BehaviorRSQQ'CS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 7S R Q0 0 hold0 1 01 0 11 1 unstableState Behavior of R-S latch! Truth table of R-S latch behaviorQ Q'0 1Q Q'1 0Q Q'0 0Q Q'1 1CS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 8Theoretical R-S Latch Behavior! State Diagram" States: possible values" Transitions: changesbased on inputsQ Q'0 1Q Q'1 0Q Q'0 0Q Q'1 1SR=00SR=11SR=00SR=10SR=01SR=00SR=10SR=00SR=01SR=11 SR=11SR=10SR=01 SR=01 SR=10SR=11possible oscillationbetween states 00 and 11CS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 9Observed R-S Latch Behavior! Very difficult to observe R-S latch in the 1-1 state" One of R or S usually changes first! Ambiguously returns to state 0-1 or 1-0" A so-called "race condition"" Or non-deterministic transitionSR=00SR=00 Q Q'0 1Q Q'1 0Q Q'0 0SR=10SR=01SR=00SR=10SR=00SR=01SR=11 SR=11SR=01 SR=10SR=11CS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 10RSQQ'Q(t+!)RSQ(t)S R Q(t) Q(t+!)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 X1 1 1 Xholdresetsetnot allowedcharacteristic equationQ(t+!) = S + R’ Q(t)R-S Latch Analysis! Break feedback path0 01 0X 1X 1Q(t)RSCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 11enable'S'Q'QR'RSGated R-S Latch! Control when R and Sinputs matter" Otherwise, theslightest glitch on Ror S while enable islow could causechange in value storedSetResetS'R'enable'QQ'100CS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 12periodduty cycle (in this case, 50%)Clocks! Used to keep time" Wait long enough for inputs (R' and S') to settle" Then allow to have effect on value stored! Clocks are regular periodic signals" Period (time between ticks)" Duty-cycle (time clock is high between ticks - expressed as %of period)CS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 13clock'S'Q'QR'RSclockR' and S'changing stable changing stablestableClocks (cont’d)! Controlling an R-S latch with a clock" Can't let R and S change while clock is active (allowing R andS to pass)" Only have half of clock period for signal changes to propagate" Signals must be stable for the other half of clock periodCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 14clockRS QQ' RS QQ'RSCascading Latches! Connect output of one latch to input of another! How to stop changes from racing through chain?" Need to control flow of data from one latch to the next" Advance from one latch per clock period" Worry about logic between latches (arrows) that is too fastCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 15Master-Slave Structure! Break flow by alternating clocks (like an air-lock)" Use positive clock to latch inputs into one R-S latch" Use negative clock to change outputs with another R-S latch! View pair as one basic unit" master-slave flip-flop" twice as much logic" output changes a few gate delays after the falling edge ofclock but does not affect any cascaded flip-flopsmaster stageslave stagePP'CLKRS QQ' RS QQ'RSCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 16Set1s catchSRCLKPP'QQ'ResetMasterOutputsSlaveOutputsThe 1s Catching Problem! In first R-S stage of master-slave FF" 0-1-0 glitch on R or S while clock is high "caught" by masterstage" Leads to constraints on logic to be hazard-freemaster stageslave stagePP'CLKRS QQ' RS QQ'RSCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 1710 gatesD Flip-Flop! Make S and R complements of each other" Eliminates 1s catching problem" Can't just hold previous value (must have new value readyevery clock period)" Value of D just before clock goes low is what is stored in flip-flop" Can make R-S flip-flop by adding logic to make D = S + R' QDQQ'master stageslave stagePP'CLKRS QQ' RS QQ'CS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 18QDClk=1RS0D’0D’DQ’negative edge-triggered D flip-flop (D-FF)4-5 gate delaysmust respect setup and hold time constraints to successfullycapture inputcharacteristic equationQ(t+1) = Dholds D' whenclock goes lowholds D whenclock goes lowEdge-Triggered Flip-Flops! More efficient solution: only 6 gates" sensitive to inputs only near edge of clock signal (not while high)CS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 19QDClk=0RSDD’D’D’Dwhen clock goes high-to-lowdata is latchedwhen clock is lowdata is heldEdge-Triggered Flip-Flops (cont’d)! Step-by-step analysisQnew DClk=0RSDD’D’D’Dnew D # old DCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 20QDClk=1RSDD’D’D’DEdge-Triggered Flip-Flops (cont’d)! D = 0, Clk High01000011Hold stateAct as invertersCS 150 - Spring 2007 – Lec. #5 – Sequential Logic - 210QDClk=1RSDD’D’D’DEdge-Triggered Flip-Flops (cont’d)! D = 1, Clk High01000 "10 "101101 "01 "0CS 150 - Spring 2007 – Lec. #5 –
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