Time TableObjectivesIntroduction to the CAD FlowFPGA EditorBitGenProgram HardwarePreLabLab ProcedureToolflow: FPGA EditorIntroduction to FPGA EditorSetting up an FPGA Editor ProjectNavigating an FPGA Editor ProjectThe Default DesignToolflow: BitGen and iMPACTBitGeniMPACTAugmenting the DesignLED LightshowLightshow HintsLab 1 CheckoffEECS150: Lab 1, FPGA EditorUC Berkeley College of EngineeringDepartment of Electrical Engineering and Computer Science1 Time TableASSIGNED Friday, January 22ndDUE Week 3: February 2nd− 4th, during your assigned lab section2 ObjectivesThis lab is meant to expose you to the bare-bones FPGA platform that you will be using for the rest ofthe semester. Throughout the semester, you will be introduced to a number of tools that hide the detailsof the FPGA you are working with so that you can instead focus on your design. Specifically, you willlearn how to represent circuits as text. A series of tools will then transform your textual circuit into realhardware on the FPGA. While this approach greatly increases productivity, it is often easy to forget thatyou are, in fact, designing components that will be mapped to actual hardware. After working throughthis lab, you will take away with you knowledge of the hardware platform that you are using so that youcan make informed design and optimization decisions throughout the rest of the course.3 Introduction to the CAD FlowFigure 1 shows the CAD tool flow that you will be using in this lab.The starting point is the ∗.ncd1design file. As you will learn in future labs, this file is generatedby the MAP and PAR (place and route) processes that play a part in translating your textual circuitdescriptions down to actual hardware. Don’t worry about MAP/PAR for now; we will be working withtheir output (the ∗.ncd file) and later steps in this lab.We will now (in Sections 3.1, 3.2 and 3.3) explain each of these CAD steps.3.1 FPGA EditorFPGA Editor is a program that allows you to make changes to a circuit that has been mapped to anactual FPGA. The FPGA, as has been discussed, is a matrix of components and wired interconnects.FPGA Editor allows you to look at exactly which of these components are currently in use, how theyare being used, and how they have been connected.FPGA Editor takes a ∗.ncd formatted file as its input. Specifically, the ∗.ncd file represents a circuitthat is mapped to a specific FPGAs resources and components. Aside from knowing what this file issupposed to contain, its details are unimportant. What is important is that FPGA Editor mo difies the∗.ncd file based on changes that you decide to make to the circuit. After these changes are made, themodified ∗.ncd is used by the BitGen pro ce ss to manufacturer a ∗. bit file.Notice in Figure 1 that the output of MAP/PAR also connects directly to BitGen as opposed togoing through FPGA Editor. This is the typical path that your designs will take this semester: we will1Native circuit description.1Figure 1 FPGA Editor tool flow.010110001001001101000101010100100101MAP/PARFPGA EditorBitGeniMPACT.ncd.ncd.bit.ncdDesign On-boardProvided by Stafftrust the so-called PAR process to do its job better than we can, and not check on its output throughFPGA Editor ourselves.3.2 BitGenWhile the ∗.ncd is a file that describes a circuit mapped to an FPGA, it isn’t in a format that the FPGAcan understand. The idea behind BitGen is simple: translate the ∗.ncd into a simpler format that issupposed to be loaded directly to the FPGA. The result of this process is a ∗.bit file that correspondsto the ∗.ncd3.3 Program HardwareOnce the ∗. bit file has been created, the last step in the story is loading the contents of the ∗. bit fileonto the actual FPGA. This is conceptually a very simple step, however, it requires detailed knowledgeof the programming cable and the FPGA. We will use a specialized tool to program the board for us.In this class we’ll be using a Xilinx Platform Cable USB II, which is really nothing more than a ratherfancy, expensive wire to connect the program, iMPACT, to the FPGA. iMPACT will then downloadthe ∗. bit file into the FPGA, thereby completing the implementation process.Once this step is complete, our design is running on actual hardware and we can ob-serve/debug/use it on the XUPv5 boards.4 PreLabPlease make sure to complete the prelab before you attend your lab section. This week’s lab will be verylong and frustrating if you do not do the prelab ahead of time.21. Read the Configurable Logic Blocks section of the Virtex-5 FPGA User Guide.(a) Pay close attention to the Virtex-5 SLICE (particularly the SLICEL), CLB (ConfigurableLogic Blocks), where to find the LUTs within the SLICE, and the FPGA fabric that connectsall of the pieces together.(b) Answer questions 1a through 1e on the back of this lab (the answers are in thereading!).2. Read Section 3 above, please make sure you understand it and ask questions ahead of time ifnecessary.3. Get a cs150-XX account form from your TA and change your Unix and Windows password to anew password of your choosing. (This can be done at the beginning of your first lab session.)(a) You must change your Windows password so that you can login to the lab computers in 125Cory (which are Windows computers).(b) You must also change your Unix password for when you are given an SVN2account later inthe semester.5 Lab ProcedureIn this lab, you will use a tool called FPGA Editor to manipulate logic and nets in a simple design.Throughout the lab, you will verify that your work in FPGA Editor is correct by programming yourFPGA with your design file and seeing it come to life in hardware. For simple verification purposes, allexercises in this lab will connect DIP switches to LEDs with some logic placed in between the two. Forexample, the design file we have provided for you as a starting point implements the logical or of twoDIP switches and shows the result on an LED (as shown in Figure 5.3). In other words, when at leastone of the two DIP Switches is turned to the ‘On’ position, the LED will light up. If neither of the DIPSwitches are ‘on,’ the LED will remain off.5.1 Toolflow: FPGA EditorBefore we start working with FPGA Editor, we will first cover how to move your design from FPGAEditor to ac tual hardware. You will be moving your designs through various tools throughout the courseof the lab and you will become intimately familiar with the process throughout the semester. Note:We have included
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