Evolution of Implementation TechnologiesGate Array Technology (IBM - 1970s)Programmable LogicProgrammable Logic TechnologiesSlide 5Making Large Programmable Logic CircuitsField-Programmable Gate ArraysSlide 8Tradeoffs in FPGAsAltera EPLD (Erasable Programmable Logic Devices)Altera EPLDAltera Multiple Array Matrix (MAX)LAB ArchitectureP22V10 PALActel Programmable Gate ArraysActel Logic ModuleActel InterconnectActel Routing ExampleXilinx Programmable Gate ArraysSlide 20The Xilinx 4000 CLBTwo 4-input functions, registered output5-input function, combinational outputCLB Used as RAMFast Carry LogicXilinx 4000 InterconnectSwitch MatrixXilinx 4000 Interconnect DetailsGlobal Signals - Clock, Reset, ControlXilinx 4000 IOBXilinx FPGA Combinational Logic ExamplesXilinx FPGA Combinational LogicXilinx FPGA Adder ExampleComputer-Aided DesignCAD Tool Path (cont’d)Xilinx CAD ToolsApplications of FPGAsXilinx FPGAs - 1trend toward higher levels of integrationEvolution of Implementation TechnologiesDiscrete devices: relays, transistors (1940s-50s)Discrete logic gates (1950s-60s)Integrated circuits (1960s-70s)e.g. TTL packages: Data Book for 100’s of different partsMap your circuit to the Data Book partsGate Arrays (IBM 1970s)“Custom” integrated circuit chipsDesign using a library (like TTL)Transistors are already on the chipPlace and route software puts the chip together automatically+ Large circuits on a chip+ Automatic design tools (no tedious custom layout)- Only good if you want 1000’s of partsXilinx FPGAs - 2Gate Array Technology (IBM - 1970s)Simple logic gatesUse transistors toimplement combinationaland sequential logicInterconnectWires to connect inputs andoutputs to logic blocksI/O blocksSpecial blocks at peripheryfor external connectionsAdd wires to make connectionsDone when chip is fabbed“mask-programmable”Construct any circuitXilinx FPGAs - 3Programmable LogicDisadvantages of the Data Book methodConstrained to parts in the Data BookParts are necessarily small and standardNeed to stock many different partsProgrammable logicUse a single chip (or a small number of chips)Program it for the circuit you wantNo reason for the circuit to be smallXilinx FPGAs - 4Programmable Logic TechnologiesFuse and anti-fuseFuse makes or breaks link between two wiresTypical connections are 50-300 ohmOne-time programmable (testing before programming?)Very high densityEPROM and EEPROMHigh power consumptionTypical connections are 2K-4K ohmFairly high densityRAM-basedMemory bit controls a switch that connects/disconnects two wiresTypical connections are .5K-1K ohmCan be programmed and re-programmed in the circuitLow densityXilinx FPGAs - 5Programmable LogicProgram a connectionConnect two wiresSet a bit to 0 or 1Regular structures for two-level logic (1960s-70s)All rely on two-level logic minimizationPROM connections - permanentEPROM connections - erase with UV lightEEPROM connections - erase electricallyPROMsProgram connections in the _____________ planePLAsProgram the connections in the ____________ planePALsProgram the connections in the ____________ planeXilinx FPGAs - 6Making Large Programmable Logic CircuitsAlternative 1 : “CPLD”Put a lot of PLDS on a chipAdd wires between them whose connections can be programmedUse fuse/EEPROM technologyAlternative 2: “FPGA”Emulate gate array technologyHence Field Programmable Gate ArrayYou need:A way to implement logic gatesA way to connect them togetherXilinx FPGAs - 7Field-Programmable Gate ArraysPALs, PLAs = 10 - 100 Gate EquivalentsField Programmable Gate Arrays = FPGAsAltera MAX FamilyActel Programmable Gate ArrayXilinx Logical Cell Array100 - 1000(s) of Gate Equivalents!Xilinx FPGAs - 8Field-Programmable Gate ArraysLogic blocksTo implement combinationaland sequential logicInterconnectWires to connect inputs andoutputs to logic blocksI/O blocksSpecial logic blocks at periphery of device forexternal connectionsKey questions:How to make logic blocks programmable?How to connect the wires?After the chip has been fabbedXilinx FPGAs - 9Tradeoffs in FPGAsLogic block - how are functions implemented: fixed functions (manipulate inputs) or programmable?Support complex functions, need fewer blocks, but they are bigger so less of them on chipSupport simple functions, need more blocks, but they are smaller so more of them on chipInterconnectHow are logic blocks arranged?How many wires will be needed between them?Are wires evenly distributed across chip?Programmability slows wires down –Oare some wires specialized to long distances?How many inputs/outputs must be routed to/from each logic block?What utilization are we willing to accept? 50%? 20%? 90%?Xilinx FPGAs - 10Clk MUXOutput MUXQF/B MUXInv ert ControlAND ARRAYCLKpad8 Product TermAND-OR Array+ProgrammableMUX'sProgrammable polarityI/O PinSeq. LogicBlockProgrammable feedbackAltera EPLD (Erasable Programmable Logic Devices)Historical PerspectivePALs: same technology as programmed once bipolar PROMEPLDs: CMOS erasable programmable ROM (EPROM) erased by UV lightAltera building block = MACROCELLXilinx FPGAs - 11Altera EPLDs contain 8 to 48 independently programmed macrocellsPersonalizedby EPROMbits:Flipflop controlledby global clock signallocal signal computesoutput enableFlipflop controlledby locally generatedclock signal+ Seq Logic: could be D, T positive or negative edge triggered+ product term to implement clear functionSynchronous ModeAsynchronous ModeGlobal CLKOE/Local CLKEPROM Cell1Global CLKOE/Local CLKEPROM Cell1Clk MUXClk MUXQQAltera EPLDXilinx FPGAs - 12LAB A LAB HLAB B LAB GLAB CLAB FLAB DLAB EP I AAND-OR structures are relatively limited Cannot share signals/product terms among macrocellsLogicArrayBlocks(similar tomacrocells)Global Routing:ProgrammableInterconnectArray8 Fixed Inputs52 I/O Pins8 LABs16 Macrocells/LAB32 Expanders/LABEPM5128:Altera Multiple Array Matrix (MAX)Xilinx FPGAs - 13LAB ArchitectureExpander Terms shared among allmacrocells within the LABMacrocell ARRAYI/O BlockExpander Product Term ARRAYI NPUTSP I AI/O PadI/O PadMacrocell P-TermsExpander P-TermsXilinx FPGAs - 140ASYNCHRONOUS RE S E T ( TO ALL REGISTERS)23AR8813217622026430835239644222OUTPUT LOGIC MACROCE LLP - 5 81 0 R - 58
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