DOC PREVIEW
Berkeley COMPSCI 150 - Lecture 2 - Synchronous Digital Systems Review Part 1

This preview shows page 1-2-3-4-5 out of 14 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 14 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

Spring 2010 EECS150 lec02-SDS-review1Page EECS150 - Digital DesignLecture 2 - Synchronous Digital Systems Review Part 1January 21, 2010John WawrzynekElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www-inst.eecs.berkeley.edu/~cs1501Spring 2010 EECS150 lec02-SDS-review1Page Outline• Topics in the review, you have already seen in CS61C, and possibly EE40:1. Digital Signals.2. General model for synchronous systems.3. Combinational logic circuits 4. Flip-flops, clocking (Next week)2Spring 2010 EECS150 lec02-SDS-review1Page Integrated Circuit Example• PowerPC microprocessor micro-photograph– Superscalar (3 instructions/cycle)– 6 execution units (2 integer and 1 double precision IEEE floating point)– 32 KByte Instruction and Data L1 caches– Dual Memory Management Units (MMU)– External L2 Cache interface with integrated controller and cache tags.Comprises only transistors and wires.Connections to outside world (ex. motherboard)• Memory interface• Power (Vdd, GND)• Clock input3Spring 2010 EECS150 lec02-SDS-review1Page Clock SignalA source of regularly occurring pulses used to measure the passage of time.• Waveform diagram shows evolution of signal value (in voltage) over time.• Usually comes from an off-chip crystal-controlled oscillator. • One main clock per chip/system. • Distributed throughout the chip/system.• “Heartbeat” of the system. Controls the rate of computation by directly controlling all data transfers.Τ represents the time of one clock “cycle”.4Spring 2010 EECS150 lec02-SDS-review1Page Data SignalsThe facts:1. Low-voltage represents binary 0 and high-voltage, binary 1.2. Circuits are design and built to be “restoring”. Deviations from ideal voltages are ignored. Outputs close to ideal.3. In synchronous systems, all changes follow clock edges.Random adder circuit at a random point in time:Observations:1. Most of the time, signals are in either low- or high-voltage position.2. When the signals are at the high- or low-voltage positions, they are not all the way to the voltage extremes (or they are past).3. Changes in the signals correspond to changes in clock signal (but don’t change every cycle).5Spring 2010 EECS150 lec02-SDS-review1Page Circuit DelayDigital circuits cannot produce outputs instantaneously.• In general, the delay through a circuit is called the propagation delay. It measures the time from when inputs arrive until the outputs change.• The delay amount is a function of many things. Some out of the control of the circuit designer:– Processing technology, the particular input values.• And others under her control:– Circuit structure, physical layout parameters.6Spring 2010 EECS150 lec02-SDS-review1Page Bus SignalsSignal wires grouped together often called a bus.•X0 is called the least significant bit (LSB)•X3 is called the most significant bit (MSB)• Capital X represents the entire bus.– Here, hexadecimal digits are used to represent the values of all four wires.– The waveform for the bus depicts it as being simultaneiously high and low. (The hex digits give the bit values). The waveform just shows the timing. 7Spring 2010 EECS150 lec02-SDS-review1Page Combinational Logic Blocks• Example four-input function:• True-table representation of function. Output is explicitly specified for each input combination.• In general, CL blocks have more than one output signal, in which case, the truth-table will have multiple output columns.a b c d y0 0 0 0 F(0,0,0,0)0 0 0 1 F(0,0,0,1)0 0 1 0 F(0,0,1,0)0 0 1 1 F(0,0,1,1)0 1 0 0 F(0,1,0,0)0 1 0 1 F(0,1,0,1)0 1 1 0 F(0,1,1,0)1 1 1 1 F(0,1,1,1)1 0 0 0 F(1,0,0,0)1 0 0 1 F(1,0,0,1)1 0 1 0 F(1,0,1,0)1 0 1 1 F(1,0,1,1)1 1 0 0 F(1,1,0,0)1 1 0 1 F(1,1,0,1)1 1 1 0 F(1,1,1,0)1 1 1 1 F(1,1,1,1)8Spring 2010 EECS150 lec02-SDS-review1Page Example CL Block• 2-bit adder. Takes two 2-bit integers and produces 3-bit result.• Think about true table for 32-bit adder. It’s possible to write out, but it might take a while!a1 a0b1 b0c2 c1 c000000000001001001001000110110100001010101001100110111100100001010010111010100101110111000111101100111010111111109Theorem: Any combinational logic function can be implemented as a networks of logic gates. Spring 2010 EECS150 lec02-SDS-review1Page Logic “Gates”ab c00 001 010 011 1ANDab c00 001 110 111 1OR NOTa b0 11 0ab c00 101 110 111 0NANDab c00 101 010 011 0NORab c00 001 110 111 0XOR• Logic gates are often the primitive elements out of which combinational logic circuits are constructed. – In some technologies, there is a one-to-one correspondence between logic gate representations and actual circuits.– Other times, we use them just as another abstraction layer (FPGAs have no real logic gates).• How about these gates with more than 2 inputs?• Do we need all these types?10Spring 2010 EECS150 lec02-SDS-review1Page Example Logic Circuit11• How do we know that these two representations are equivalent?a b c y0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1Spring 2010 EECS150 lec02-SDS-review1Page Logic Gate Implementation• Logic circuits have been built out of many different technologies. As we know, as long as we have a basic logic gate (AND or OR) and inversion we can build any a complete logic family. 12CMOS GateDTLHydraulic Mechanical LEGO logic gates. A clockwise rotation represents a binary “one” while a counter-clockwise rotation represents a binary “zero.”Spring 2010 EECS150 lec02-SDS-review1Page Restoration• An necessary property of any successful technology for logic circuits is "Restoration".• Circuits need:– to ignore noise and other non-idealities at the their inputs, and– generate "cleaned-up" signals at their output.• Otherwise, each stage would propagates input noise to their output and eventually noise and other non-idealities would accumulate and signal content would be lost.13Spring 2010 EECS150 lec02-SDS-review1Page Inverter Example of Restoration• Inverter acts like a “non-linear” amplifier• The non-linearity is critical to restoration• Other logic gates act similarly with respect to input/output relationship.14Example (look at 1-input gate, to keep it simple):Idealize InverterActual InverterSpring 2010 EECS150 lec02-SDS-review1Page Abstract View of MIPS Implementation15DataOutclk5Rw Ra RbRegisterFileRdData


View Full Document

Berkeley COMPSCI 150 - Lecture 2 - Synchronous Digital Systems Review Part 1

Documents in this Course
Lab 2

Lab 2

9 pages

Debugging

Debugging

28 pages

Lab 1

Lab 1

15 pages

Memory

Memory

13 pages

Lecture 7

Lecture 7

11 pages

SPDIF

SPDIF

18 pages

Memory

Memory

27 pages

Exam III

Exam III

15 pages

Quiz

Quiz

6 pages

Problem

Problem

3 pages

Memory

Memory

26 pages

Lab 1

Lab 1

9 pages

Memory

Memory

5 pages

Load more
Download Lecture 2 - Synchronous Digital Systems Review Part 1
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Lecture 2 - Synchronous Digital Systems Review Part 1 and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lecture 2 - Synchronous Digital Systems Review Part 1 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?