Time TableObjectivesAddendum to the CAD FlowDesign EntryDesign PartitioningTranslate, Map, Place and RouteTranslateMapPlacementRoutingPPR: Partitioning vs. Place and RouteAfter PAR: Design Tuning and Device ConfigurationLab PrerequisitesAllowed Verilog ConstructsUsing Xilinx FPGA PrimitivesStructural AccumulatorCoding the AccumulatorPreLabLab ProcedureCircuit DebuggingProject SetupRunning Synplify: Syntax Checking and Schematic GenerationHardware VerificationCircuit AnalysisResource AnalysisTiming AnalysisReferencesLab 2 CheckoffEECS150: Lab 2, Mapping Circuit Elements to FPGAsUC Berkeley College of EngineeringDepartment of Electrical Engineering and Computer ScienceFebruary 4, 20091 Time TableASSIGNED Friday, January 30thDUE Week 4: February 8th− 14th, 10 minutes after your lab section starts2 ObjectivesIn this lab, you will be working with Verilog HDL (hardware description language) to architect a practicalcircuit. After designing your circuit, you will debug and verify it using a hardware-based test harness.Finally, after your circuit is working correctly, you will conduct a resource and timing analysis that willshow you exactly how your design was actually implemented on the FPGA.Through conducting these tests, you will gain experience working with non-trivial circuits on realhardware. Additionally, you will learn about design partitioning, the process where primitive gates andflip-flops in an HDL, like Verilog, are mapped down to primitive elements on the FPGA. Lastly, youwill learn how to use hardware-based test harnesses, along with various tools, to help you debug yourdesigns.3 Addendum to the CAD FlowIn the FPGA Editor lab, you learned how a file1that contains a circuit description, m apped to a specificFPGA, can be modified and used to configure actual hardware. In this lab, we will be exploring anextension to this CAD flow that, in the end, generates the circuit description file. As in last lab, we willuse the .ncd to generate a .bit file which we will then use to verify our design in hardware.Figure 1 shows the additions to the tool flow that we will be using in this lab. The parts of the flow inthe gray box were explored in the FPGA Editor lab. In this exercise, you will be introduced to DesignEntry (Section 3.1), Design Partitioning (Section 3.2) and Translate/Map/PAR (Section 3.3).Collectively, Design Partitioning and PAR are known as Partition-Place-and-Route or PPR. It is inthese steps that you will be performing a majority of your analysis.3.1 Design EntryThe first step in logic design is to conceptualize your design. Once you have a good idea about the functionand structure of your circuit and maybe a few block diagram sketches, you can start the implementationprocess by specifying your circuit in a more formal manner.In this class we will use a Hardware Description Language (HDL) called Verilog. HDLs have severaladvantages over other methods of circuit specification:1. Ease of editing, since files can be written using any text editor1Specifical ly, we are referring to the .ncd file that FPGA Editor works with.1Figure 1 Structural Verilog −→ .bit file tool flow.010110001001001101000101010100100101Translate/Map/PARFPGA EditorBitGen iMPACT.ncd.ncd.ncd (optionally modified).bitDesign PartitioningDesign EntryVerilog HDL Synplify ProPrevious Lab (FPGA Editor)Optional step2. Ease of management when dealing with large designs3. The ability to use a high-level behavioral description of a circuit.In this class we will default to using basic text editors to write Verilog. Fancier editors are available,and in fact are included with the CAD tools such as Xilinx ISE and ModelSim; howe ver these tools areslow and will often hinder you. In this lab, you will only be using a small subset of Verilogcalled Structural Verilog. Specifically, you will be designing down to primitive gates (such as and andor) and flip-flops.3.2 Design PartitioningDesign partitioning is the process of transforming the primitive gates and flip-flops that you wrote inVerilog into LUTs and other primitive FPGA elements. For example, if you described a circuit composedof many gates, but ultimately of 6 inputs and 1 output, Design Partitioning will map your circuit downto a single 6LUT. Likewise, if you described a flip-flop, it will be mapped to a specific type of flip-flopwhich actually exists on the FPGA. The final product of the design partitioning phase is a netlist file, atext file that contains a list of all the instances of primitive components in the translated circuit and adescription of how they are connected.3.3 Translate, Map, Place and RouteFrom the netlist produced by the design partitioning tools, we must somehow create a file that can bedirectly translated into a bitstream to configure the FPGA. This is the job of the Translate, Map, andthe Place and Route (PAR) tools.3.3.1 TranslateTranslate takes as input a netlist file from the design partitioning tools and outputs a Xilinx database file,which is the same thing as the netlist, reduced to logic elements expressed in terms that Xilinx-specificdevices can understand.3.3.2 MapMap takes as input the database file which was output from Translate and ‘maps’ it to a specific XilinxFPGA. This is necessary because different FPGAs have different architectures, resources, and compo-nents.23.3.3 PlacementPlacement takes as input the result of the “Map” step and determines exactly where, physically, on theFPGA each LUT, flip-flop, and logic gate should be placed. For example, a 6LUT implementing thefunction of a 6-input NAND gate in a netlist could be placed in any of the 69,120 6LUTs in a XilinxVirtex5 xc5vlx110t FPGA chip. Clever choice of placement will make the subsequent routing easier andresult a circuit with less delay.3.3.4 RoutingOnce the components are placed, the proper connections must be made. This step is called routing,because the tools must choose, for e ach signal, one of the millions of paths to get that signal from itssource to its destination.Because the number of possible paths for a given signal is very large, and there are many signals, thisis typically the most time consuming part of implementing a design, aside from specification. Planningyour design well and making it compact and efficient will significantly reduce how long this step takes.Designing your circuit well can cut the time it takes to route from 30 min to 30 sec.3.3.5 PPR: Partitioning vs. Place and RouteUnlike design partitioning, which only needs
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