DOC PREVIEW
Berkeley COMPSCI 150 - Using ChipScope

This preview shows page 1-2 out of 5 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 5 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 5 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 5 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

EECS Fall 2008 Using Chip Scope UCB Page 1 UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Using ChipScope Overview ChipScope is an embedded, software based logic analyzer. By inserting an “integrated controller core” (icon) and an “integrated logic analyzer” (ila) into your design and connecting them properly, you can monitor any or all of the signals in your design. Even nicer is that ChipScope provides you with a convenient software based interface for controlling the “integrated logic analyzer,” including setting the triggering options and viewing the waveforms. ChipScope has a few disadvantages however. First, because it is synchronous ChipScope cannot be used to examine clock signals. Second, because it uses the SRAM on the Virtex part, it cannot capture very many samples. There are six main steps to using ChipScope, as detailed below. 1. Setup a CORE Generator project 2. Generate an “integrated controller core” or icon 3. Generate one or maybe more “integrated logic analyzers” or ilas 4. Connect the ilas to the icon and make all of these modules part of your design. 5. Synthesize, and implement your design (including the icon and ila) as normal. 6. Program the CaLinx board 7. Run the ChipScope software to access and use the ilas (the ChipScope software requires the icon to gain access to the ilas) Detailed Instructions: Step 1 – Creating a new Project 1. Open Start  Programs  Xilinx ISE Design Suite 10.1  ISE  Accessories  CORE Generator. 2. Open File  New Project. a. Choose where to save project files. i. Create a new directory and open it. ii. Save the coregen.cgp file in this directory. iii. This is where your ICON and ILA cores (and their metadata files) will be generated. b. Under the Part tab, select all of the same device settings as you do when you setup a normal Xilinx ISE Project. c. Under the Generation tab, change Design Entry to Verilog. d. Select Ok to return to the main screen. 3. On the main screen, go to the View By Function tab. a. Select the Debug and Verification folder.EECS Fall 2008 Using Chip Scope UCB Page 2 b. Select Chip Scope Pro. 4. You should now be looking at a list of Chip Scope “cores.” Among them should be ICON, ILA, and VIO. We will be using ICONs and ILAs. Detailed Instructions: Step 2 – Generating the ICON 1. Double-click on ICON (ChipScope Pro – Integrated Controller). A window that will allow you to customize your ICON should have appeared. a. Component Name: Assign your ICON a name (this is arbitrary). b. Select the correct Number of Control Ports. i. Each ILA requires one control port ii. Normally you will only need 1 Control Port iii. If you generate an ICON with multiple control ports, you must connect every control port to an ILA. If you have “hanging” control ports in your design, Xilinx ISE will fail during synthesis. c. Leave Disable Boundary Scan unchecked. d. Leave Enable Unused Boundary Scan Ports unchecked. 2. The ChipScope Pro Core Generator will now generated the ICON core according to the settings you specified. If you have errors go back and make sure you followed the above instructions. 3. Click Finish to Return to the main screen. 4. Your ICON will have been created in the directory you specified to store your project. Detailed Instructions: Step 3 – Generating the ILA 1. Once again on the main screen, double-click on ILA (ChipScope Pro – Integrated Logic Analyzer). A window that will allow you to customize your ILA should have appeared. a. Component Name: Same as with the ICON, you may set this to whatever you like. As the semester progresses, you will see what an informative ILA naming convention entails. b. Normally you will only need 1 Trigger Port c. Leave Enable Output Trigger Port unchecked. d. Leave Sample On to Rising (you will sample on the rising edge). e. Select the desired Sample Data Depth i. This is the number of samples the ILA will capture after it receives the trigger. It will capture one sample per clock cycle until it captures this many samples. You will probably need relatively few for Lab5. f. Leave Data Same as Trigger unchecked. i. The bench logic analyzers in the lab have 16bits of input used for both the data and the trigger. The ILA can have separate data and trigger inputs. For clarity’s sake this semester, always have different trigger and data ports. In Lab5, if you use a “detected error” signal then you should connect that to the trigger and connect the counter output to the data port.EECS Fall 2008 Using Chip Scope UCB Page 3 g. Data Port Width is only available when you are using separate trigger and data ports. Set this to the number of bits you will need to see in the wave window of ChipScope. h. (CLICK NEXT TO GO TO THE NEXT PAGE) i. Set the Trigger Port Width to any amount you desire (probably either 1bit or 32bits for Lab5) j. You will most likely need 1 Match Unit. k. Leave Counter Width to Disabled. l. Leave Match Type set to basic. 2. The ChipScope Pro Core Generator will now generated the ICON core according to the settings you specified. If you have errors go back and make sure you followed the above instructions. 3. Click Finish to Return to the main screen. 4. Your ILA will have been created in the directory you specified to store your project. Detailed Instructions: Step 4 – Connecting the Cores to Your Design 1. Declare a control bus for each ILA, similar to the following: a. wire [35:0] ILAControl; b. Remember, each ILA you want to add to your design will require a control bus. c. You can route control busses as input/outputs if you want to instantiate the ICON somewhere other than where you instantiate the ILA. 2. Instantiate the ICON core a. icon i_icon(.CONTROL0(ILAControl)); b. Remember to only instantiate ONE ICON, your design can never have more than one. 3. Instantiate the ILA core a. ila i_ila(.CONTROL(ILAControl), .CLK(Clock), .TRIG0(/**/), .DATA(/**/)); b. You may instantiate ILAs wherever they are necessary, just make sure to route the control bus from the ICON appropriately c. You may have one or more ILAs in your design. d. Your ILA may have different ports be sure to read the verilog example produced by the ChipScope Core


View Full Document

Berkeley COMPSCI 150 - Using ChipScope

Documents in this Course
Lab 2

Lab 2

9 pages

Debugging

Debugging

28 pages

Lab 1

Lab 1

15 pages

Memory

Memory

13 pages

Lecture 7

Lecture 7

11 pages

SPDIF

SPDIF

18 pages

Memory

Memory

27 pages

Exam III

Exam III

15 pages

Quiz

Quiz

6 pages

Problem

Problem

3 pages

Memory

Memory

26 pages

Lab 1

Lab 1

9 pages

Memory

Memory

5 pages

Load more
Download Using ChipScope
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Using ChipScope and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Using ChipScope 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?