UC Regents Fall 2011 © UCBCS 150 L14: DRAM2011-10-13Elad Alontoday’s lecture by John LazzaroCS 150 Digital DesignLecture 14 – DRAMwww-inst.eecs.berkeley.edu/~cs150/TAs: Daiwei Li, James Parker, Dan Yeager1UC Regents Fall 2011 © UCBCS 150 L14: DRAMToday’s Lecture: DRAMDRAM: Bottom-upDRAM, Xilinx, and YouDRAM: Top-downFigure 4: 64 Meg x 8 Functional Block Diagram 14Row-addressMUXControllogicColumn-addresscounter/latchMode registers10Command decodeA0–A13,BA0, BA114Addressregister16256(x32)8,192I/O gatingDM mask logicColumndecoderBank 0Memoryarray(16,384 x 256 x 32)Bank 0row-addresslatch anddecoder16,384Sense amplifiersBankcontrollogic16Bank 1Bank 2Bank 314822Refreshcounter8882RCVRS323232CK outDataDQS, DQS#internalCK, CK#CK, CK#COL0, COL1COL0, COL1CK inDRVRSDLLMUXDQSgenerator88888DQ0–DQ7DQS, DQS#2ReadlatchWriteFIFOanddriversData8888321111Mask111114882Bank 1Bank 2Bank 3InputregistersDMRDQS#RAS#CAS#CKCS#WE#CK#CKEODTRDQSVddQR1R1R2R2sw1sw2VssQsw1sw2ODT controlsw3R3R3sw3R1R1R2R2sw1sw2R3R3sw3R1R1R2R2sw1sw2R3R3sw3Figure 5: 32 Meg x 16 Functional Block Diagram 13Row-addressMUXControlLogicColumn-addresscounter/latchModeregisters10A0–A12,BA0, BA113Addressregister15256(x64)16,384I/O gatingDM mask logicColumndecoderBank 0Memoryarray(8,192 x 256 x 64)Bank 0row-Addresslatch anddecoder8,192Sense amplifiersBankcontrollogic15 Bank 1Bank 2Bank 313822Refreshcounter1616164646464CK outDataUDQS, UDQS#LDQS, LDQS#InternalCK, CK#CK, CK#COL0, COL1COL0, COL1CK inDLLMUXDQSgenerator1616161616UDQS, UDQS#LDQS, LDQS#4ReadlatchWriteFIFOanddriversData16161616642222Mask22222816162Bank 1Bank 2Bank 3InputregistersUDM, LDMDQ0–DQ15RAS#CAS#CKCS#WE#CK#Command decodeCKEODTDRVRSRCVRSVddQR1R1R2R2sw1sw2VssQsw1sw2ODT controlsw3R3R3sw3R1R1R2R2sw1sw2R3R3sw3R1R1R2R2sw1sw2R3R3sw3512Mb: x4, x8, x16 DDR2 SDRAMFunctional Block DiagramsPDF: 09005aef82f1e6e2512MbDDR2.pdf - Rev. O 7/09 EN12Micron Technology, Inc. reserves the right to change products or specifications without notice.©2004 Micron Technology, Inc. All rights reserved.2UC Regents Fall 2011 © UCBCS 150 L14: DRAM14 www.xilinx.com ML505/ML506/ML507 Evaluation PlatformUG347 (v3.0) May 19, 2008Chapter 1: ML505/ML506/ML507 Evaluation PlatformRNote: The label on the CompactFlash (CF) card shipped with your board might differ from the one shown.Figure 1-3: Detailed Description of Virtex-5 ML505 Components (Back)UG347_02_11290617214332343DDR2 SO-DIMM on ML505 BoardDDR2: Double-Data Rate, 2nd generationSO-DIMM: Small-Outline, Dual Inline Memory Module3UC Regents Fall 2011 © UCBCS 150 L14: DRAMDDR2 SO-DIMM ModuleDDR2 SDRAM SODIMMMT4HTF1664HY – 128MBMT4HTF3264HY – 256MBMT4HTF6464HY – 512MBFeatures!200-pin, small-outline dual in-line memory module(SODIMM)!Fast data transfer rates: PC2-3200, PC2-4200,PC2-5300, or PC2-6400!128MB (16 Meg x 64), 256MB (32 Meg x 64), or512MB (64 Meg x 64)!VDD = VDDQ = 1.8V!VDDSPD = 1.7–3.6V!JEDEC-standard 1.8V I/O (SSTL_18-compatible)!Differential data strobe (DQS, DQS#) option!4n-bit prefetch architecture!Multiple internal device banks for concurrent opera-tion!Programmable CAS latency (CL)!Posted CAS additive latency (AL)!WRITE latency = READ latency - 1 tCK!Programmable burst lengths (BL): 4 or 8!Adjustable data-output drive strength!64ms, 8192-cycle refresh!On-die termination (ODT)!Serial presence detect (SPD) with EEPROM!Gold edge contacts!Single rankFigure 1: 200-Pin SODIMM (MO-224 R/C C)Module height: 30mm (1.18in)OptionsMarking!Operating temperature "Commercial (0°C # TA # +70°C)None"Industrial (–40°C # TA # +85°C)1I!Package "200-pin DIMM (lead-free)Y!Frequency/CL2 "2.5ns @ CL = 5 (DDR2-800)-80E"2.5ns @ CL = 6 (DDR2-800)-800"3.0ns @ CL = 5 (DDR2-667)-667"3.75ns @ CL = 4 (DDR2-533)3-53E"5.0ns @ CL = 3 (DDR2-400)3-40ENotes:1.Contact Micron for industrial temperaturemodule offerings.2.CL = CAS (READ) latency.3.Not recommended for new designs.Table 1: Key Timing ParametersSpeedGradeIndustryNomenclatureData Rate (MT/s)tRCD(ns)tRP(ns)tRC(ns)CL = 6CL = 5CL = 4CL = 3-80EPC2-6400 800 800 533 400 12.5 12.5 55-800PC2-6400 800 667 533 400 15 15 55-667PC2-5300"667 553 400 15 15 55-53EPC2-4200" "553 400 15 15 55-40EPC2-3200" "400 400 15 15 55128MB, 256MB, 512MB (x64, SR) 200-Pin DDR2 SODIMMFeaturesPDF: 09005aef8161d160htf4c16_32_64x64h.pdf - Rev. I 3/10 EN1Micron Technology, Inc. reserves the right to change products or specifications without notice.© 2005 Micron Technology, Inc. All rights reserved.Products and specifications discussed herein are subject to change by Micron without notice.Functional Block DiagramFigure 2: Functional Block Diagram BA[2/1:0]A[12:0]RAS#CAS# WE# CKE0 ODT0 BA[2/1:0]: DDR2 SDRAM A[12:0]: DDR2 SDRAM RAS#: DDR2 SDRAM CAS#: DDR2 SDRAM WE#: DDR2 SDRAM CKE0: DDR2 SDRAM ODT0: DDR2 SDRAM DDR SDRAM U1, U2CK0CK0#DDR SDRAM U3, U4CK1CK1#A0Serial PDA1A2SA0SA1SDASCLWPU5VREFVSSDDR2 SDRAM DDR2 SDRAM VDDVDDSPDSerial PDDDR2 SDRAM DQS DQS# DM DQDQ DQ DQ DQ DQDQDQ DQS DQS# DM DQ DQDQDQ DQ DQ DQDQDQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15DQS0 DQS0# DM0DQS1 DQS1# DM1CS#U1DQS DQS# DM DQDQ DQ DQ DQ DQDQDQ DQS DQS# DM DQ DQDQDQ DQ DQ DQDQDQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31DQS2 DQS2# DM2DQS3 DQS3# DM3CS#U2DQS DQS# DM DQDQ DQ DQ DQ DQDQDQ DQS DQS# DM DQ DQDQDQ DQ DQ DQDQDQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47DQS4 DQS4# DM4DQS5 DQS5# DM5CS#U3DQS DQS# DM DQDQ DQ DQ DQ DQDQDQ DQS DQS# DM DQ DQDQDQ DQ DQ DQDQDQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63DQS7 DQS7# DM7DQS6 DQS6# DM6CS#U4S0#3VSSVSS128MB, 256MB, 512MB (x64, SR) 200-Pin DDR2 SODIMMFunctional Block DiagramPDF: 09005aef8161d160htf4c16_32_64x64h.pdf - Rev. I 3/10 EN6Micron Technology, Inc. reserves the right to change products or specifications without notice.© 2005 Micron Technology, Inc. All rights reserved.DRAM chipsare wired in parallel and run in lockstep.4UC Regents Fall 2011 © UCBCS 150 L14: DRAMProject controller: Xilinx-supplied IPMemory Interface Solutions User Guide www.xilinx.com 137UG086 (v3.6) September 21, 2010Direct-Clocking InterfaceRDDR2 Controller SubmodulesInfrastructureThe infrastructure module generates the FPGA clock and reset signals. When differential clocking is used, sys_clk_p, sys_clk_n, clk_200_p, and clk_200_n signals appear. When single-ended clocking is used, sys_clk and idly_clk_200 signals appear. In addition, clocks are available for design use and a 200 MHz clock is provided for the IDELAYCTRL
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