1EECS 150 Spring 2003Lab Lecture 4Verilog Design Synthesis2/13/2003Sandro Pintz MOTIVATION Finite State Machine Design Design Partitioning Design Entry Synthesis Mapping, Placing and Routing2“Think Hardware (1)”If(a == 1) Z= A + B;Else Z= A + C;if(a == 1) aux = B;else aux = C;Z = A + aux;CaB1A01ZaA01auxZBC“Think Hardware (2)”assign B = 3;assign Z = A * B;assign Z = A + 2 * A;BZA<<AZn+1 bit adder3“Think Hardware (3)”auxA[n-1:1]Zn bit adderAA[0]assign aux = {1'b0, A[n-1:1]} + A[n-1:0];assign Z = {aux, A[0]};Simulation (1) Event Driven Simulation Order of execution in time tick is not fixed Simulator dependent (ouch!) Deadlocks can happen in perfectly good design Simulation and Synthesis can differ functionally4Execution Order Time Slice: Q1 — (in any order) : Evaluate RHS of all non-blocking assignments Evaluate RHS and change LHS of all blocking assignments Evaluate RHS and change LHS of all continuous assignments Evaluate inputs and change outputs of all primitives Evaluate and print output from $display and $write Q2 — (in any order) : Change LHS of all non-blocking assignments Q3 — (in any order) : Evaluate and print output from $monitor and $strobe Call PLI with reason_synchronize Q4 : Call PLI with reason_rosynchronizeSimulation (2)always @() beginnxstate = state;case(state)3'b000: beginout = 1'b1;nxstate = 3'b101;end3'b001: beginout = 1'b0;end3'b100: beginout = 1'b1;end3'b101: beginendendcaseend Two possible state transitionsDifferent outputs Who holds the value of out?000001100101out = 1out = 1out = 0out = 0 or 15Blocking vs Non-Blocking (1)always @() begina = b;c = a;endalways @() begina <= b;c <= a;end Result: a = b = c Result a = b and c = old aBlocking vs Non-Blocking (2)always @(posedge clock) beginb <= #1 a; /* b and c will be flip flops */ c <= #1 b; end Use Non-Blocking for Flop Inference: They are always synthesized as FFUse #1 to visual causality!6Blocking vs Non-Blocking (3)always @(posedge clock) begin b = a; /* Only c will be a flip flop, */c = b; /* b will go away after synthesis. */end /* ‘b’ is not needed at all */If you use Blocking for Flop Inference:You might not get what you thinkalways @(posedge clock) begin c = b; /* c and b will be flip flops, */b = a; end Blocking vs Non-Blocking (4)file xyz.v : module xyz(a,b,clk); input b,clk; output a; reg a; always @(posedge clk) a = b; endmodule file abc.v : module abc(b,c,clk); input c, clk; output b; reg b; always @(posedge clk) b = c; endmodule Race Conditions7Combination LockInput SignalDescriptionRESET Clear any entered numbersENTER Read the switches (enter a number in the combination)CODE[1:0] Two binary switchesOutputsignalDescriptionOPEN Lock opensERROR Incorrect combinationCombLockResetEnterCode2OpenErrorPartitioningResetEnterCode2OpenErrorCompareSTART[ERR OR= 0OP EN=0]OK1[ER ROR= 0OPEN= 0]BAD1[ERROR=0OPEN=0]OK2[ERROR=0OPEN=1]BAD2[ERR OR= 1OPEN =0]ENTER'ENTER'ENTER'ENTER & COM 1ENTER & COM 1'ENTER & COM2'ENTER &COM2ENTERcom1com2De-bounce8State Machine Transition DiagramSTART[ERROR=0OPEN=0]OK1[ERROR=0OPEN=0]BAD1[ERROR=0OPEN=0]OK2[ERROR=0OPEN=1]BAD2[ERROR=1OPEN=0]ENTER'ENTER'ENTER'ENTER & COM1ENTER & COM1'ENTER & COM2'ENTER
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