Berkeley COMPSCI 150 - Lab Lecture 4 (8 pages)

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Lab Lecture 4



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Lab Lecture 4

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Pages:
8
School:
University of California, Berkeley
Course:
Compsci 150 - Components and Design Techniques for Digital System...
Components and Design Techniques for Digital System... Documents
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EECS 150 Spring 2003 Lab Lecture 4 Verilog Design Synthesis 2 13 2003 Sandro Pintz MOTIVATION Finite State Machine Design Design Partitioning Design Entry Synthesis Mapping Placing and Routing 1 Think Hardware 1 If a 1 Z A B Else Z A C B A C 11 0 a Z if a 1 aux B else aux C Z A aux A B C 1 0 a aux Z Think Hardware 2 A assign B 3 assign Z A B Z A assign Z A 2 A B n 1 b it a d d e r Z 2 Think Hardware 3 assign aux 1 b0 A n 1 1 A n 1 0 assign Z aux A 0 A n 1 1 A n b it a d d e r A 0 aux Z Simulation 1 Event Driven Simulation Order of execution in time tick is not fixed Simulator dependent ouch Deadlocks can happen in perfectly good design Simulation and Synthesis can differ functionally 3 Execution Order Time Slice Q1 in any order Evaluate RHS of all non blocking assignments Evaluate RHS and change LHS of all blocking assignments Evaluate RHS and change LHS of all continuous assignments Evaluate inputs and change outputs of all primitives Evaluate and print output from display and write Q2 in any order Change LHS of all non blocking assignments Q3 in any order Evaluate and print output from monitor and strobe Call PLI with reason synchronize Q4 Call PLI with reason rosynchronize Simulation 2 always begin nxstate state case state 3 b000 begin out 1 b1 nxstate 3 b101 end Two possible state transitions Different outputs Who holds the value of out 3 b001 begin out 1 out 1 b0 end 000 3 b100 begin out 1 b1 end out 0 001 100 out 1 3 b101 begin end endcase end 101 out 0 or 1 4 Blocking vs Non Blocking 1 always begin a b c a Result a b c end always begin a b Result a b and c old a c a end Blocking vs Non Blocking 2 Use Non Blocking for Flop Inference They are always synthesized as FF Use 1 to visual causality always posedge clock begin b 1 a b and c will be flip flops c 1 b end 5 Blocking vs Non Blocking 3 If you use Blocking for Flop Inference You might not get what you think always posedge clock begin b a Only c will be a flip flop c b b will go away after synthesis end always posedge clock begin c b c and b will be flip flops b a end b is not needed at all Blocking vs Non Blocking 4 Race Conditions file xyz v module xyz a b clk input b clk output a reg a always posedge clk a b endmodule file abc v module abc b c clk input c clk output b reg b always posedge clk b c endmodule 6 Combination Lock Input Signal Description RESET Clear any entered numbers ENTER Read the switches enter a number in the combination CODE 1 0 Two binary switches Output signal Description OPEN Lock opens ERROR Incorrect combination Open Reset Enter Code Comb Lock Error 2 Partitioning Open com1 Code 2 Compare ENTER ENTER COM1 com2 Reset ERROR 0 OP EN 0 ENTER E NTER C OM2 OK2 ENTER COM1 BAD1 ENTER COM2 ERROR 0 OP EN 1 Enter START O K1 ER ROR 0 OPEN 0 ERROR 0 OPEN 0 E NTER BAD2 ERR OR 1 OPEN 0 ENTER Error Debounce 7 State Machine Transition Diagram ENTER ENTER COM1 START ERROR 0 OPEN 0 OK1 ERROR 0 OPEN 0 ENTER BAD1 ENTER COM2 ENTER COM2 OK2 ENTER COM1 ERROR 0 OPEN 1 ERROR 0 OPEN 0 ENTER ENTER BAD2 ERROR 1 OPEN 0 8


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