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Berkeley COMPSCI 150 - UART Adapter (Mini‐Project)

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UART Adapter (Mini‐Project)UART Adapter (MiniProject)UCB EECS150 Spring 2010Lab Lecture#5Lab Lecture #51UCB EECS150 Spring 2010, Lab Lecture #5AgendaAgenda•TheentireCS150 CAD flowThe entireCS150 CAD flow• A new debugging tool (ChipScope)b i b d i i• Lab 5 is to be done in pairsQuestions?• A very awkward picture of Chris asleep in a car•Lab 5 overviewLab 5 overview• Design reviews2UCB EECS150 Spring 2010, Lab Lecture #5Where we are andwhyWhere we are and why3UCB EECS150 Spring 2010, Lab Lecture #5New tool :ChipScope(1)SoftwareNew tool : ChipScope(1)•In‐System DebuggerInSystem Debugger• “ModelSim in hardware”• But has many limitationsbleSame Clock!y• Samples signalson clock edgeYour Ci itDual Port MJTAG CabTriggeron clock edge• Shows only a few cyclesChi SCircuitMemorycycles• Trigger‐basedChipScopeFPGA4UCB EECS150 Spring 2010, Lab Lecture #5ChipScope(2)ChipScope(2)•Is not“Magic”Is not Magic• Uses block memories on the FPGA to save the value of a signal. Saves several cycles after trig gered (a pre‐determined input pattern occurs)• Software reads and displays the saved trace• Know its limitations!• Expensive• Can affect timing• Gives limited visibility5UCB EECS150 Spring 2010, Lab Lecture #5ChipScope(3)ChipScope(3)Compared to ModelSim:• ModelSim• High visibility (shows any, or every signal in the design).•Quick turnaround for debuggingQu c tu a ou d o debugg g• Only a simulation (not guaranteed to work in hardware)• Will not show all bugs•ChipScopeChipScope• Shows values observed in hardware (the real deal)• Samplesthe data using a clock•Requires a complete tool cycle for debugging•Requires a complete tool cycle for debugging• Low visibility (shows only a small number of signals)!USE BOTH!6UCB EECS150 Spring 2010, Lab Lecture #5New Policy (Lab 5 and Project)New Policy (Lab 5 and Project)•A design document must be shown1 weekA design document must be shown 1 week before check ‐off in your lab section.–Both partners must be present–Both partners must be present.– Be prepared to defend your designThis is a part of your grade–This is a part of your grade– Stay tuned (detail in a few slides)• Pick a partner for Lab 5!UCB EECS150 Spring 2010, Lab Lecture #5 7Lab 5 is a Partner Lab!Lab 5 is a Partner Lab!•Find someone to work with!Find someone to work with!• Must pick a partner by FridayN b d f thki–Newsgroup can be used for match‐making– Can pick a different partner for the project8UCB EECS150 Spring 2010, Lab Lecture #5Questions?Questions?•CS150 CADToolflowCS150 CAD Toolflow• ChipScope, ModelSimhi f b j• Partnerships for Lab 5, Project• Anything else?9UCB EECS150 Spring 2010, Lab Lecture #5Please Don’t Sleep in the LabPlease Don t Sleep in the Lab•It’s uncomfortableIt s uncomfortable• It’s embarrassinghi bd• 4 chairs ≠ bed• It’s just plain bad for youGo home to sleep!Go home to sleep!UCB EECS150 Spring 2010, Lab Lecture #5 10Lab 5 (Mini‐Project)(1)Lab 5 (MiniProject)(1)Small part of theprojectppjUART interface and a little something to test itSMIPS CPUMemory MapGraphics AcceleratorInstruction MemoryData MemoryDVI Video InterfaceEthernet InterfaceUART (Serial) InterfaceSRAM InterfaceFrame Buffer(SRAM)FPGAUCB EECS150 Spring 2010, Lab Lecture #5 11Lab 5 (Mini‐Project)(2)Lab 5 (MiniProject)(2)•Use the entiretoolflowCPU EmulatorState MachineUse the entire toolflow– Labs 1‐4 taught you how•Learn to use a handshakeState MachineAdapter•Learn to use a handshake• Build a state machine to mimic a CPUUART Interface–To test the UART Interface• We give you a UART module– Understand it intimately•Practice creating design documentsPractice creating design documents12UCB EECS150 Spring 2010, Lab Lecture #5Lab 5 (Mini‐Project)(3)Lab 5 (MiniProject)(3)XUPv5Software SideConsole Interface(0xffff_000c-0xffff_0000)UARTMIPS150 Processor EmulatorPutty/Hyper-terminalDataAddressRS-232/Serial PortVirtex-5 LX110T FPGARS-232 Serial CableUCB EECS150 Spring 2010, Lab Lecture #5 13Ready‐Valid Handshake(1)ReadyValid Handshake(1)•Synchronous flow controlSynchronous flow contr ol– Synchronizes the flow of data(within one clock domain)(within one clock domain)• Creates a stream abstraction• Other handshakes exist– But we like this oneUCB EECS150 Spring 2010, Lab Lecture #5 14Ready‐Valid Handshake(2)ReadyValid Handshake(2)• A transfer from A to B occurs when:ta sfeo to occu s e:– A positive edge of the clock arrives– and B is asserting Ready– and A is asserting Valid• No sequence requirements• Upon a transfer:– B may look at the Data (save, etc.)Clock–A must either:• de‐assert valid•Expose the next DatumClockReadyValidDtExpose the next DatumUCB EECS150 Spring 2010, Lab Lecture #5 15DataTransfersProcedureProcedure1) Read the specification2) DO NOT WRITE ANY VERILOG YET!3) Draw a very high‐level block diagram (be neat and name everything)everything)4) Expand blocks into new diagrams until you understand all details.5)Find design flaws and repeat steps 145)Find design flaws and repeat steps 1‐4.6) Think of ways to verify (test) the design.7) Show your design to the TAs. Be prepared to defend it.8) Now implement and verify the designUCB EECS150 Spring 2010, Lab Lecture #5 16Design Documents(1)Design Documents(1)•Spend 2+hours on thisSpend 2 hours on this– Detailed enough for someone else to implement–Show structure and function (no screenshots)( )– Use hierarchy and omit detail (no mess o’ wires)–Xfig, OmniGraffle, Visio, et c. (no MSPaintplease)g,, , (p)– Document all optimizations and hacks thoroughly• A good design document will make g gimplementation and debugging easy– Else you will pull an all‐nighter.UCB EECS150 Spring 2010, Lab Lecture #5 17Design Documents(2)Design Documents(2)• Graded out of 3 points:pClear Understandable What?210Solid idea An idea No ideaPast CS150 designs deserve a 1.Many commercial datasheets deserve a 0.UCB EECS150 Spring 2010, Lab Lecture #5 18Acknowledgements & ContributorsAcknowledgements & ContributorsSlides developed by Ilia Lebedev & John Wawrzynek (2/2010).This work is based in part on slides by:Ilia Lebedev Chris Fletcher (2008‐2009)Ilia Lebedev, Chris Fletcher (20082009)Greg Gibeling (2003‐2005)hi k h b d b h fll iThis work has been used by the following courses:– UC Berkeley CS150 (Spring 2010): Components and Design Techniques for Digital Systems 19UCB EECS150


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Berkeley COMPSCI 150 - UART Adapter (Mini‐Project)

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