University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS 150 Spring 2002 Lab 7 (Project Checkpoint #1) UART Design 1 Objective In this lab you will design, simulate, implement, and test the receiver portion of a universal asynchronous receiver / transmitter circuit (UART). This circuit will be useful later for your course project, but more importantly, through its design you will gain more experience with the FPGA device. 2 Functional Specification UARTs are used for communication between two devices. For instance, UARTs are used to connect terminals to computers. UARTs are also used in systems using MIDI. They provide a means to send data with a minimum of wires. The data is sent bit-serially, and no clock signal is sent along with it. The primary function of a UART is parallel-to-serial conversion when transmitting, and serial-to-parallel conversion when receiving. The fact that a clock is not transmitted with the data complicates the design of a UART. The two systems (sender and receiver) have separate, unsynchronized, clock signals. Although the two clocks will have the same frequency, they will not have the same phase. Part of a UART’s function, and the tricky part, is to “sample” the serial input at just the right time to reliably capture the bit stream. A high-speed clock to sample the bit stream multiple times per data bit allows one to accomplish this task. In our application the bit transfer rate, or baud rate, is 31.25kHz. This rate is the standard for MIDI devices and will be useful later for the course project. Your FPGA board is equipped with a 16MHz crystal oscillator. To generate a 31.25kHz clock signal divide the crystal oscillator frequency by 512. We do not actually need that frequency for this lab. The frequency we need is 8 times the MIDI baud rate: 8 × (31.25kHz) = 250kHz. Figure 1 shows a functional block diagram of the UART receiver that you will design. Bit-serial data is received on the SERIAL-IN.H input. When one byte of data has been received, it is output to the D output bus, and the output control signal DRDY.H is asserted for one clock period. The block is clocked with a frequency 8 times the baud rate, in this case 250kHz. The reset signal RESET.H and output enable OE.H are optional.Data is transferred one byte at a time to the receiver using the format shown in Figure 2. The transmission character is composed of an 8-bit data byte, sent LSB first, preceded by a start bit (LOW) and followed by a stop bit (HIGH). When no character is being transmitted, the line is idle (HIGH). The line need not go idle between characters, as it is possible for the start bit of a transmission to immediately follow the stop bit of the previous transmission. 3 Theory of Operation This section describes the internal operation of the UART receiver that you will design. There are many possible detailed designs – we will not present them all here, but we will give you some ideas. The simplest solution for receiving transmission characters is to generate a clock signal at the baud rate, in this case 31.25KHz, and to use it to clock the bits one at a time into a serial-to-parallel converter. A serial-to-parallel converter is simply a shift-register with its internal flip flops connected directly to outputs. For help on describing a shift register in Verilog, use “Language Assistant” feature in HDL Editor. In general, the following code generates a shift register that operates on the positive clock edge: reg [3:0] out; always @(posedge clk) begin out = {in, out[3:1]}; end UART D[7:0] DRDY.H RESET.H OE.LSERIAL-IN.HClock Figure 1: UART symbol. Start Idle D0 D1 D2 D3 D4 D5 D6 D7 Stop Idle Time Figure 2: A MIDI transmission character.The key to understanding this code is the concatenation operator, specified by curly braces. All signals enumerated inside the braces are joined together to form one “bus”. A counter can be used to build a simple controller which counts-off the ten bits of a transmission character (start, 8 data bits, and stop), generates the data ready signal DRDY.H, then resets itself. Counters are available in the Xilinx FPGA component library, but none are primitive to XC4000X part and therefore cannot be instantiated directly. We suggest that you develop your own counter, which may include some of the features of the library counters. For example, some counters are loadable with an initial starting value. Non-loadable counters count from 0. Normal operation of a non-loadable counter, after being reset, is to count from 0 to 2n–1 (1 increment per cycle), then to wrap around and start counting at 0 again. Loadable counters are used to count through fewer than 2n values, by starting at an initial count other than zero and reaching the maximum count sooner. Some counters in the library have a terminal count (TC) output signal, which is set high on the cycle when the counter reaches its maximum value 2n–1. In this application, the actual Q values of the counter need not be used, only the TC signal. With the proper input to a loadable counter, the TC signal can be made to assert once every 10 clock cycles – exactly what we need for the DRDY.H signal. TC can also be used to reset the counter by enabling the load of the initial count value into the counter. Take a look at the data-sheet for the “Serial-in Parallel-out” shift register SR8RE in the Xilinx Library Guide (available from Xilinx’s web site as well as our course web page). It is instructive to start by sketching out a simple UART design based on this component and a 4-bit counter. If you have the time, you might want to implement your design in Verilog and test it out in the lab. You will find is that it has unreliable behavior. Because the receiver clock is out of phase with the sender clock, it is possible for the circuit to capture input bits when they are not at valid logic values, i.e. during transitions. The way we will build a reliable receiver is to start with a high-speed clock signal, in this case 8x the baud-rate clock, 250kHz. This clock is used to super-sample the input waveform. A stage is used to determine the clock period when the start bit is approximately “half-way” transmitted. This can be
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