CS 150 - Spring 2007 – Lec #10: Memory Controller - 1SDRAM Memory Controller! Static RAM Technology" 6T Memory Cell" Memory Access Timing! Dynamic RAM Technology" 1T Memory Cell" Memory Access TimingCS 150 - Spring 2007 – Lec #10: Memory Controller - 2Tri-State GatesOE_LINOUT+0IN OUTOE_LOUTINOE_LOE_LINOUT+0InX01OE_L100OutZ01CS 150 - Spring 2007 – Lec #10: Memory Controller - 3Slick Multiplexer ImplementationOUTIN0IN1S2:1 MultiplexerS01OutIN0IN1CS 150 - Spring 2007 – Lec #10: Memory Controller - 4Basic Memory Subsystem Block DiagramAddressDecoderWord Linen AddressBits2n wordlinesm Bit LinesMemorycellwhat happensif n and/or m isvery large?CS 150 - Spring 2007 – Lec #10: Memory Controller - 5Static RAM Cell! Write:" 1. Drive bit lines (bit=1, bit=0)" 2. Select row! Read:" 1. Precharge bit and bit to Vdd or Vdd/2 => make sure equal!" 2.. Select row" 3. Cell pulls one line low" 4. Sense amp on column detects difference between bit and bit6-Transistor SRAM Cellbit bitword(row select)bit bitwordreplaced with pullupto save area100 1CS 150 - Spring 2007 – Lec #10: Memory Controller - 6Typical SRAM Organization: 16-word x 4-bitSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCellSRAMCell- +Sense Amp- +Sense Amp- +Sense Amp- +Sense Amp: : : :Word 0Word 1Word 15Dout 0Dout 1Dout 2Dout 3- +Wr Driver &Precharger- +Wr Driver &Precharger- +Wr Driver &Precharger- +Wr Driver &PrechargerAddress DecoderWrEnPrechargeDin 0Din 1Din 2Din 3A0A1A2A3CS 150 - Spring 2007 – Lec #10: Memory Controller - 7! Write Enable is usually active low(WE_L)! Din and Dout are combined tosave pins:" A new control signal, output enable(OE_L) is needed" WE_L is asserted (Low), OE_L isdisasserted (High)# D serves as the data input pin" WE_L is disasserted (High), OE_L isasserted (Low)# D is the data output pin" Both WE_L and OE_L are asserted:# Result is unknown. Don’t do that!!!ADOE_L2Nwordsx M bitSRAMNMWE_LLogic Diagram of a Typical SRAMCS 150 - Spring 2007 – Lec #10: Memory Controller - 8Typical SRAM TimingWrite Timing:DRead Timing:WE_LAWriteHold TimeWrite Setup TimeADOE_L2Nwordsx M bitSRAMNMWE_LData InWrite AddressOE_LHigh ZRead AddressJunkRead AccessTimeData OutRead AccessTimeData OutRead AddressOE determines direction Hi = Write, Lo = ReadWrites are dangerous! Be careful! Double signaling: OE Hi, WE LoCS 150 - Spring 2007 – Lec #10: Memory Controller - 9Problems with SRAM! Six transistors use up lotsof area! Consider a “Zero” is storedin the cell:" Transistor N1 will try to pull“bit” to 0" Transistor P2 will try to pull“bit bar” to 1! Bit lines are already pre-charged high: Are P1 and P2really necessary?bit = 1 bit = 0Select = 1On OffOff OnN1 N2P1 P2OnOnCS 150 - Spring 2007 – Lec #10: Memory Controller - 101-Transistor Memory Cell (DRAM)! Write:" 1. Drive bit line" 2. Select row! Read:" 1. Precharge bit line to Vdd/2" 2. Select row" 3. Cell and bit line share charges# Minute voltage changes on the bit line" 4. Sense (fancy sense amp)# Can detect changes of ~1 million electrons" 5. Write: restore the value! Refresh" 1. Just do a dummy read to every cellrow selectbitRead is really aread followed bya restoring writeCS 150 - Spring 2007 – Lec #10: Memory Controller - 11Classical DRAM Organization (Square)rowdecoderrowaddressColumn Selector & I/O CircuitsColumnAddressdataRAM Cell Arrayword (row) selectbit (data) lines! Row and Column Address together:" Select 1 bit a timeEach intersection representsa 1-T DRAM CellSquare keeps the wires short:Power and speed advantagesLess RC, faster precharge anddischarge is faster access time!CS 150 - Spring 2007 – Lec #10: Memory Controller - 12DRAM Logical Organization (4 Mbit)! Square root of bits per RAS/CAS" Row selects 1 row of 2048 bits from 2048 rows" Col selects 1 bit out of 2048 bits in such a rowColumn DecoderSense Amps & I/OMemory Array(2,048 x 2,048)A0…A10…11DQWord LineStorage CellROWDECODER114 Mbit = 22 address bits 11 row address bits 11 col address bitsAddress BufferBit LineData InData OutCS 150 - Spring 2007 – Lec #10: Memory Controller - 13ADOE_L256K x 8DRAM9 8WE_L! Control Signals (RAS_L, CAS_L, WE_L, OE_L) are all active low! Din and Dout are combined (D):" WE_L is asserted (Low), OE_L is disasserted (High)# D serves as the data input pin" WE_L is disasserted (High), OE_L is asserted (Low)# D is the data output pin! Row and column addresses share the same pins (A)" RAS_L goes low: Pins A are latched in as row address" CAS_L goes low: Pins A are latched in as column address" RAS/CAS edge-sensitiveCAS_LRAS_LLogic Diagram of a Typical DRAMCS 150 - Spring 2007 – Lec #10: Memory Controller - 14ADOE_L256K x 8DRAM9 8WE_LCAS_LRAS_LOE_LA Row AddressWE_LJunkRead AccessTimeOutput EnableDelayCAS_LRAS_LCol Address Row Address JunkCol AddressD High Z Data OutDRAM Read Cycle TimeEarly Read Cycle: OE_L asserted before CAS_LLate Read Cycle: OE_L asserted after CAS_L! Every DRAM access begins at:" Assertion of the RAS_L" 2 ways to read: early or late v. CASJunk Data Out High ZDRAM READ TimingCS 150 - Spring 2007 – Lec #10: Memory Controller - 15Early Read Sequencing! Assert Row Address! Assert RAS_L" Commence read cycle" Meet Row Addr setup time before RAS/hold time after RAS! Assert OE_L! Assert Col Address! Assert CAS_L" Meet Col Addr setup time before CAS/hold time after CAS! Valid Data Out after access time! Disassert OE_L, CAS_L, RAS_L to end cycleCS 150 - Spring 2007 – Lec #10: Memory Controller - 16Sketch of Early Read FSMRow Address to MemoryAssert RAS_LSetup time met?FSM Clock?Assert OE_L, RAS_LCol Address to MemoryHold time met?Assert OE_L, RAS_L, CAS_LSetup time met?Hold time met?Assert OE_L, RAS_L, CAS_LData Available (better grab it!)CS 150 - Spring 2007 – Lec #10: Memory Controller - 17Late Read Sequencing! Assert Row Address! Assert RAS_L" Commence read cycle" Meet Row Addr setup time before RAS/hold time after RAS!Assert Col Address!Assert CAS_L"Meet Col Addr setup time before CAS/hold time after CAS! Assert OE_L! Valid Data Out after access time! Disassert OE_L, CAS_L, RAS_L to end cycleCS 150 - Spring 2007 – Lec #10: Memory Controller - 18Sketch of Late Read FSMRow Address to MemoryAssert RAS_LSetup time met?FSM Clock?Col Address to MemoryAssert RAS_LHold time met?Col Address to MemoryAssert RAS_L, CAS_LSetup time met?Hold time met?Assert OE_L, RAS_L, CAS_LData Available (better grab it!)CS 150 - Spring 2007 – Lec #10: Memory Controller -
View Full Document