University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences CS 150, Spring 2001 J. Wawrzynek, N. Weaver Modified by R. Fearing, D. Young, and N. Aboobaker Xilinx F3.0 Version, New library: Laura Todd Lab 3 Finite State Machine on Xilinx 1 Objective Put your combination lock from Lab 2 onto a chip. To do this, you will: 1. Use Xilinx Flow Engine to compile and route your design. 2. Use Xilinx Hardware Debugger to do real-time hardware debugging and watch internal signals 1.1 Overview Figure 1. Steps taken in this lab to compile, download, and test design For a design to be useful, it must make its way into hardware. To do this we will be using Xilinx Field Programmable Gate Arrays (FPGAs), chips that can be configured as many different circuits. Specifically, we will be using the Xilinx XC4000 Design Demonstration Board, which contains an XC4010XL FPGA, switches, and light-emitting diodes. These boards are very expensive and not easily replaced. Be very careful with these. Make sure that they stay on the anti-static mat. Make sure also that the ground plug is plugged in. Before touching the Xilinx board, ground yourself-- touch any metal you can find or the static mat. Do not take the Xilinx boards or anything else from 204B Cory! Schematic Editor (Create Netlist, Integrity Test, and Export Netlist) Implementation (Compiling and Routing Design) Hardware Debugger (Downloading to Chip + Debugging)2 Prelab 1. Answer the questions on the checkoff sheet. 2. Make sure your Lab 2 design works and the labels in your schematic match the labels shown in the example from Lab 2. Your STATE bits should be wired as a bus. 3. Also check that none of your filenames are longer than 8 characters. We're using new software so this might or might not be a problem (it's better to be safe though). 4. Make sure your schematic does not use any components from the built-in library. If you followed the instructions in Lab 2, this should not be a problem. 5. Make sure none of your symbols or components have the same name as components in the (XC4010XLPC84) library, such as DFF or CLB. If you did, rename your components. 2.1 Xilinx Interface To compile your design for the Xilinx, some interface components need to be added. We have done the busy work for you. (See section 3.1 below) 2.1.1 I/O Pads I/O pads and buffers are special cells in the (XC4010XLPC84) library, and connect the Xilinx to the outside world of buttons, LEDs, and other chips: IPAD Input Pad OPAD Output Pad IBUF Input Buffer OBUF Output Buffer Each IPAD and OPAD is connected to a particular pin on the Xilinx, designated by the LOC attribute. For example, in our schematic, the IPAD in the upper-left corner, SW5-7, has the attribute LOC=P27, indicating it connects to pin 27 of the Xilinx. 2.1.2 Debounce Your lock expects ENTER and RESET to be high for exactly one clock cycle every time it is pressed. The DEBOUNCE circuit, a simple state machine, ensures this. 3 Add the Xilinx Interface Circuits We have entered the required interface circuits as a macro; you need to add the macro to your design. You need to add the TA-provided library and add the macro to your combination lock schematic. As with one-sheet schematics, nets with the same label on different sheets of the same schematic are connected implicitly, but nets inside a macro are not implicity connected to nets outside the macro. 1. The TA macro library must be added to your library list to make access to some of the symbols possible. Select File àà Project Libraries… (or ctrl + L), then, if a library called library is in the list on the left, select it and click on “Add >>”. If it isn’t in the list, click on “Lib Manager…”. Select Library àà Attach…, and go to U:\cs150\. A library called library should appear in the right list window. Press OK. The Project Libraries window should come back up with the library you just added in the list window on the left. Click on the new library, then click on “Add>>” to add it to your project libraries. As a check, make sure it has shown up in your project manager file list. Note: Windows NT has problems when many people access the same file at once. To avoid this error, us the Lib Manager’s “Copy Library” function and copy the library files to your home directory. 2. In the Symbol Toolbox there should be a new set of symbols: Debounce, etc. Choose the one called IO and add it to your Lab 2 combination lock schematic. Connect the pins of the IO macro to the correct signals from your combination lock. 3. Convert your chip type: In the Project Manager window, click on the “File” menu, then choose the “Project Type” dialog. Change the “Flow” to “XC4000XL” and change the chip type to “4010XLPC84”. 4. From the schematic editor, run Options àà Create netlist, Options àà Integrity test, and Options àà export netlist.4 Preparing your Schematic to be downloaded to hardware The next step after successfully exporting your netlist is preparing it for downloading to the chip. The Xilinx Flow Engine, which is started by clicking on the Implementation box (located under the Design Entry box), will compile and route the exported (EDIF) netlist into a bit file that can be downloaded to the Xilinx chip. A new window will pop up showing the progress of the compilation and routing. To look at the results of a compilation, click on the “Versions” tab in your project manager, right click on the revision that you need information on, and select “View Implementation Log” or “Invoke Interactive Flow Engine”. Both will show you a log of the compilation. You can also access the log by clicking on the “Reports” tab and double clicking on “Implementation Log File”. Look through the log and see what information it gives you. There is a tool that let you see graphically the resulting mapping of the logic in the Xilinx chip. Select Tools àà Implementation àà FPGA Editor. Choose File->Open and open an implementation to see how it is layed out on the Xilinx chip. You should take a look, since it's pretty neat to see. By selecting nets in the list, you can see how the compiler has routed
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