EECS 150 Fall 2007 Lab 0 UCB 1 2007 UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 0 Chips, Scopes, and Analyzers ASSIGNED: Week of 8/27 DUE: Week of 9/2, 10 minutes after start of your assigned lab section. 1.0 Motivation In this lab you will gain hands-on experience with simple combinational gates (the real version of what you met in simulation on 61C) breadboarding simple circuits and using the basic tools of hardware design – signal generators and oscilloscopes. In future labs, you will be “wiring up” circuits by programming your FPGA. This lab will give you a little bit of experience with traditional gates and insight toward what is going on inside the FPGA. Also, in debugging hardware you will often resort of using (or building) tools that generate certain patterns and observing how your hardware behaves when presented with those patterns. 2.0 Introduction to TTL In this lab you will use a single 74C00 quad NAND gate in a Dual Inline Package (DIP). You will gain some experience using the tools on your lab bench. First, we will use the power supply and multimeter to observe the combinational behavior of a simple chip. Using the four gates that come in a 7400 package, you’ll build and verify a simple combinational circuit. Second, we will utilize the function generator and oscilloscope to observe its timing behavior. Third, we will “break the rules” for combination logic and build a simple sequential circuit – a ring oscillator – by creating a cycle of combinational logic. Finally, we’ll build a sequential circuit that is useful for synchronous digital logic design – a latch. 3.0 Prelab There is no prelab preparation for this lab. Your TA will explain the operation of the materials described below. You will consult the associated documentation as you work through the lab. Materials 1. Breadboard 2. HP 8116A Pulse/Function Generator 3. HP 54645D Mixed Signal Oscilloscope 4. HP E3630A DC Power Supply 5. 74C00 quad NAND chip 6. ProbesEECS 150 Fall 2007 Lab 0 UCB 2 2007 4.0 Lab Procedure Receive you CS150 account from your lab TA. Log in and verify that your account works. (A) Logical Behavior 1. Go on the web and find the datasheet for the chip that you are using. Identify the pins used for power and ground, as well as the inputs and outputs of the gates. 2. Configure your power supply to provide 5V DC. Use the red COM terminal for ground. Note that this connection may not be present on some power supplies in which case the ground should be connected to the corresponding negative terminal. Verify with your multimeter that you have a 5V supply to work with before you wire it to your chip. Wire these to Vdd and GND rails of your breadboard. Wire the rails to the corresponding Vdd and Gnd pins of your 74C00. 3. Pick a NAND gate in your 74C00, identify its input pins and its output. Connect GND to the inputs of the NAND gate and capture the output using the multimeter. Repeat for the other 3 combinations of high and low inputs for the NAND gate and draw the truth table. Verify that it is the NAND function. (You can also use your oscilloscope to observe the signals.) 4. Using multiple NAND gates, configure them to implement a 2-input XOR function. Draw the circuit. Draw the truth table. Wire it up and verify that it works. Have your TA initial your checkoff. (B) Timing behavior 1. Use the pulse/function generator to create a square wave as input to the series of NAND gates. You may need to play around a little with the amplitude and offset for some of the function generators to get a proper square wave oscillating from 0V to 5V. If you are not familiar with the operation of the oscilloscope, read the summary below. Adjust the triggering and timescale so that you can see a complete cycle. Adjust the cursors so that you can read the period on the screen (press the cursors button, and then select the time/measurement cursors before using the entry knob to move them to their proper location). 2. Wire your NAND gates to form a sequence of inverters. 3. Capture the input, the output of the first gate and the output of the last gate using the oscilloscope. 4. Use the oscilloscope to measure the rise and fall times and the propagation delays in your circuit. Use the time and voltage cursors to get these measured times. 5. Find the rise and fall times and the propagation delays described in your datasheet? How do these compare to your measurements? 6. Reconfigure your circuit to have a single NAND gate driving three gates. How do the propagation times change?EECS 150 Fall 2007 Lab 0 UCB 3 2007 (C) Simple Sequential Circuit with Feedback 1. Configure your circuit to form a ring containing three NAND gates. 2. Explain the expected behavior of this circuit. 3. Estimate the period and frequency of the output 4. Capture the waveform and compare with your estimate. Have you TA initial your checkoff. (D) Simple Latch 1. Configure your circuit to form a gated SR latch with cross-coupled NAND gates. hint: http://en.wikipedia.org/wiki/Latch_(electronic) 2. What should be the behavior when the “Clock” input is high? 3. What should be the behavior when the “Clock” input is low? 4. Capture the waveform showing that it works as a latch. (You will need to think a little bit about what you are going to provide as inputs to demonstrate it behavior to your TA.) CEECS 150 Fall 2007 Lab 0 UCB 4 2007EECS 150 Fall 2007 Lab 0 UCB 5 2007 5.0 HP54645D Mixed Signal Oscilloscope (Logic Analyzer) Figure 1: HP54645D Mixed Signal Oscilloscope Shown in Figure 1 above, is the HP54645D Mixed Signal Oscilloscope, which we will generally refer to as simply “the oscilloscope” or “the logic analyzer.” It is in fact a combination of these instruments, both of which are design to graph waveforms (analog and digital respectively) over time. Using the logic analyzer is significantly less complicated than it appears and it is an invaluable debugging tool. The logic analyzer allows us to examine signals over time at various scales, you can zoom in to see events on different clock cycles, or zoom out to see how a signal behaves over
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