Spring 2009EECS150 - Lec06-CAD1Page EECS150 - Digital DesignLecture 4 - Computer Aided Design (CAD) - Part I (Logic Synthesis)Feb 5, 2009John Wawrzynek1Spring 2009EECS150 - Lec06-CAD1Page State Elements2Always blocks are the only way to specify the “behavior” of state elements. Synthesis tools will turn state element behaviors into state element instances. dsqrclkmodule dff(q, d, clk, set, rst); input d, clk, set, rst; output q; reg q; always @(posedge clk) if (reset) q <= 1’b0; else if (set) q <= 1’b1; else q <= d;endmoduleD-flip-flop with synchronous set and reset example:keyword“always @ (posedge clk)” is key to flip-flop generation.This gives priority to reset over set and set over d.On FPGAs, maps to native flip-flop.Spring 2009EECS150 - Lec06-CAD1Page Finite State Machines3State Transition DiagramImplementation Circuit DiagramHolds a symbol to keep track of which bubble the FSM is in.CL functions to determine output value and next state based on input and current state.out = f(in, current state)next state = f(in, current state)Spring 2009EECS150 - Lec06-CAD1Page Finite State Machinesmodule FSM1(clk, rst, in, out);input clk, rst;input in;output out;// Defined state encoding:parameter IDLE = 2'b00;parameter S0 = 2'b01;parameter S1 = 2'b10;reg out;reg [1:0] state, next_state;// always block for state registeralways @(posedge clk) if (rst) state <= IDLE; else state <= next_state;4Must use reset to force to initial state.reset not always shown in STDout not a register, but assigned in always blockTHE register to hold the “state” of the FSM.Combinational logic signals for transition.Constants local to this module.A separate always block should be used for combination logic part of FSM. Next state and output generation. (Always blocks in a design work in parallel.)Spring 2009EECS150 - Lec06-CAD1Page FSMs (cont.)// always block for combinational logic portionalways @(state or in) case (state)// For each state def output and next IDLE : begin out = 1’b0; if (in == 1’b1) next_state = S0; else next_state = IDLE; end S0 : begin out = 1’b0; if (in == 1’b1) next_state = S1; else next_state = IDLE; end S1 : begin out = 1’b1; if (in == 1’b1) next_state = S1; else next_state = IDLE; end default: begin next_state = IDLE; out = 1’b0; endendcaseendmodule5For each state define: Each state becomes a case clause.Output value(s)State transitionUse “default” to cover unassigned state. Usually unconditionally transition to reset state.Spring 2009EECS150 - Lec06-CAD1Page Example - Parallel to Serial Convertermodule ParToSer(ld, X, out, CLK); input [3:0] X; input ld, clk; output out; reg out; reg [3:0] Q; wire [3:0] NS; assign NS = (ld) ? X : {Q[0], Q[3:1]}; always @ (posedge clk) Q <= NS; assign out = Q[0];endmodule 6Specifies the muxing with “rotation”forces Q register (flip-flops) to be rewritten every cycleconnect outputldoutoutSpring 2009EECS150 - Lec06-CAD1Page Parameterized Version7module ParToSer(ld, X, out, CLK); input [3:0] X; input ld, clk; output out; reg out; reg [3:0] Q; wire [3:0] NS; assign NS = (ld) ? X : {Q[0], Q[3:1]}; always @ (posedge clk) Q <= NS; assign out = Q[0];endmodulemodule ParToSer(ld, X, out, CLK); input [N-1:0] X; input ld, clk; output out; reg out; reg [N-1:0] Q; wire [N-1:0] NS; assign NS = (ld) ? X : {Q[0], Q[N-1:1]}; always @ (posedge clk) Q <= NS; assign out = Q[0];endmoduleReplace all occurrences of “3” with “N-1”.parameter N = 3;Declare a parameter with default value. Note: this is not a port. Acts like a “synthesis-time” constant.ParToSer #(.N(8)) ps8 ( ... );ParToSer #(.N(64))ps64 ( ... );Overwrite parameter N at instantiation.Parameters give us a way to generalize our designs. A module becomes a “generator” for different variations. Enables design/module reuse. Can simplify testing.Spring 2009EECS150 - Lec06-CAD1Page Generate Loop8Permits variable declarations, modules, user defined primitives, gate primitives, continuous assignments, initial blocks and always blocks to be instantiated multiple times using a for-loop.// Gray-code to binary-code convertermodule gray2bin1 (bin, gray); parameter SIZE = 8; output [SIZE-1:0] bin; input [SIZE-1:0] gray; genvar i; generate for (i=0; i<SIZE; i=i+1) begin:bit assign bin[i] = ^gray[SIZE-1:i]; end endgenerate endmodule Loop must have constant boundsgenerate if-else-if based on an expression that is deterministic at the time the design is synthesized.generate case : selecting case expression must be deterministic at the time the design is synthesized. genvar exists only in the specification - not in the final circuit.Keywords that denotes synthesis-time operationsFor-loop creates instances of assignmentsSpring 2009EECS150 - Lec06-CAD1Page EECS150 Design MethodologyHDLSpecificationHierarchically define structure and/or behavior of circuit.SimulationFunctional verification.SynthesisMaps specification to resources of implementation platform (FPGA for us).9Note: This in not the entire story. Other tools are often used analyze HDL specifications and synthesis results. More on this later.Spring 2009EECS150 - Lec06-CAD1Page Logic Synthesis • Verilog and VHDL started out as simulation languages, but quickly people wrote programs to automatically convert Verilog code into low-level circuit descriptions (netlists).• Synthesis converts Verilog (or other HDL) descriptions to implementation technology specific primitives:– For FPGAs: LUTs, flip-flops, and RAM blocks– For ASICs: standard cell gate and flip-flop libraries, and memory blocks.10Spring 2009EECS150 - Lec06-CAD1Page Why Logic Synthesis?1. Automatically manages many details of the design process:⇒Fewer
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