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Berkeley COMPSCI 150 - Lecture 5 - Field Programmable Gate Arrays (FPGAs)

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EECS150 - Digital Design Lecture 5 - Field Programmable Gate Arrays (FPGAs)OutlineFPGA OverviewWhy FPGAs?Slide 5Slide 6Slide 7FPGA VariationsUser ProgrammabilityIdealized FPGA Logic Block4-LUT ImplementationLUT as general logic gateAnnouncementsFPGA Generic Design FlowExample Partition, Placement, and RouteXilinx FPGAs (4000 Series)Xilinx FPGAs (CLB detail)Xilinx FPGAs (IOB detail)Xilinx FPGAs (interconnect detail)Xilinx 4000 series FPGAsSpring 2002 EECS150 - Lec05-FPGAPage 1EECS150 - Digital DesignLecture 5 - Field Programmable Gate Arrays (FPGAs)February 4, 2002John WawrzynekSpring 2002 EECS150 - Lec05-FPGAPage 2Outline•What are FPGAs?•Why use FPGAs (a short history lesson).•FPGA variations•Internal logic blocks.•Break/Announcements•Designing with FPGAs.•Specifics of Xilinx 4000 series.Spring 2002 EECS150 - Lec05-FPGAPage 3FPGA Overview•Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure:1. the interconnection between the logic blocks,2. the function of each block.Simplified version of FPGA internal architecture:Spring 2002 EECS150 - Lec05-FPGAPage 4Why FPGAs?•By the early 1980’s most of the logic circuits in typical systems where absorbed by a handful of standard large scale integrated circuits (LSI). –Microprocessors, bus/IO controllers, system timers, ...•Every system still had the need for random “glue logic” to help connect the large ICs:–generating global control signals (for resets etc.)–data formatting (serial to parallel, multiplexing, etc.) •Systems had a few LSI components and lots of small low density SSI (small scale IC) and MSI (medium scale IC) components.Spring 2002 EECS150 - Lec05-FPGAPage 5Why FPGAs?•Custom ICs where sometimes designed to replace the large amount of glue logic:–reduced system complexity and manufacturing cost, improved performance.–However, custom ICs are relatively very expensive to develop, and delay introduction of product to market (time to market) because of increased design time. •Note: need to worry about two kinds of costs:1. cost of development, sometimes called non-recurring engineering (NRE)2. cost of manufacture–A tradeoff usually exists between NRE cost and manufacturing costst o t a lc o s t sn u m b e r o f u n i t s m a n u f a c t u r e d ( v o l u m e )N R EABSpring 2002 EECS150 - Lec05-FPGAPage 6Why FPGAs?•Therefore the custom IC approach was only viable for products with very high volume (where NRE could be amortized), and which were not TTM sensitive.•FPGAs were introduced as an alternative to custom ICs for implementing glue logic:–improved density relative to discrete SSI/MSI components (within around 10x of custom ICs)–with the aid of computer aided design (CAD) tools circuits could be implemented in a short amount of time (no physical layout process, no mask making, no IC manufacturing)•lowers NREs•shortens TTM•Because of Moore’s law the density (gates/area) of FPGAs continued to grow through the 80’s and 90’s to the point where major data processing functions can be implemented on a single FPGA.Spring 2002 EECS150 - Lec05-FPGAPage 7Why FPGAs?•FPGAs continue to compete with custom ICs for special processing functions (and glue logic) but now also compete with microprocessors in dedicated and embedded applications.–Performance advantage over microprocessors because circuits can be customized for the task at hand. Microprocessors must provide special functions in software (many cycles).•Summary:ASIC = custom IC, MICRO = microprocessorp e r f o r m a n c e N R E sU n i tc o s t T T MA S I C A S I C A S I CF P G AM I C R OF P G AM I C R OF P G AM I C R OF P G AA S I CM I C R OSpring 2002 EECS150 - Lec05-FPGAPage 8FPGA Variations•Families of FPGA’s differ in:–physical means of implementing user programmability,–arrangement of interconnection wires, and–the basic functionality of the logic blocks.•Most significant difference is in the method for providing flexible blocks and connections: •Anti-fuse based (ex: Actel)+Non-volatile, relatively small–fixed (non-reprogrammable)Spring 2002 EECS150 - Lec05-FPGAPage 9User Programmability•Latches are used to:1. make or break cross-point connections in the interconnect2. define the function of the logic blocks3. set user options:•within the logic blocks•in the input/output blocks•global reset/clock•“Configuration bit stream” can be loaded under user control:–All latches are strung together in a shift chain:•Latch-based (Xilinx, Altera, …)+reconfigurable–volatile–relatively large.l a t c hSpring 2002 EECS150 - Lec05-FPGAPage 10Idealized FPGA Logic Block•4-input look up table (LUT)–implements combinational logic functions•Register–optionally stores output of LUT4 - L U T F F10l a t c hL o g i c B l o c ks e t b y c o n f i g u r a t i o n b i t - s t r e a m4 - i n p u t " l o o k u p t a b l e "O U T P U TI N P U T SSpring 2002 EECS150 - Lec05-FPGAPage 114-LUT Implementation•n-bit LUT is implemented as a 2n x 1 memory:–inputs choose one of 2n memory locations.–memory locations (latches) are normally loaded with values from user’s configuration bit stream.–Inputs to mux control are the CLB inputs.•Result is a general purpose “logic gate”. –n-LUT can implement any function of n inputs!l a t c hl a t c hl a t c hl a t c h1 6 x 1m u x1 6I N P U T SO U T P U TL a t c h e s p r o g r a m m e d a s p a r to f c o n f i g u r a t i o n b i t - s t r e a mSpring 2002 EECS150 - Lec05-FPGAPage 12LUT as general logic gate•An n-lut as a direct implementation of a function truth-table.•Each latch location holds the value of the function corresponding to one input combination.0 0 0 0 F ( 0 , 0 , 0 , 0 )0 0 0 1 F ( 0 , 0 , 0 , 1 )0 0 1 0 F ( 0 , 0 , 1 , 0 )0 0 1 1 F ( 0 , 0 , 1 , 1 )0 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1I N P U T Ss t o r e i n 1 s t l a t c hs t o r e i n 2 n d l a t c hExample: 4-lutExample: 2-lutO RA N DI N P U T S1 1 1 11 0 0 10 1 0 10 0 0 0Implements any function of 2 inputs. How many of these are there?How many functions of n inputs?Spring 2002 EECS150 - Lec05-FPGAPage 13Announcements•Quiz results•Administrative Q&A.•New reading posted:–large section of


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Berkeley COMPSCI 150 - Lecture 5 - Field Programmable Gate Arrays (FPGAs)

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