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Berkeley COMPSCI 150 - Synchronous Digital Systems Review (Part II)

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UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems II2010-1-28John WawrzynekEECS 150 -- Digital DesignLecture 4 – Synchronous Digital Systems Review (Part II)www-inst.eecs.berkeley.edu/~cs150Today’s lecture by John Lazzaro1Thursday, January 28, 2010Spring 2010 EECS150 lec04-SDS-review2Page EECS150 - Digital DesignLecture 4 - Synchronous Digital Systems Review Part 2January 28, 2010John WawrzynekElectrical Engineering and Computer SciencesUniversity of California, Berkeleyhttp://www-inst.eecs.berkeley.edu/~cs15022Thursday, January 28, 2010Spring 2010 EECS150 lec04-SDS-review2Page Outline• Topics in the review, you have already seen in CS61C, and possibly EE40:1. Digital Signals.2. General model for synchronous systems.3. Combinational logic circuits 4. Flip-flops, clocking 33Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIToday’s LectureFlip-flop-based state machinesRegisters and PipeliningRegister-based state machinesFlip-flop details ...Operates on Boolean (single-bit) values.Operates on multi-bit values (integers, CPU instruction, ...)Adding state to speed up the clock.(Reset, set, etc ...)4Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIFlip-Flop State Machines5Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIA Simple System: Traffic Light ControllerR Y G1 0 0 R Y G0 0 1 R Y G0 1 0 Power up to red stateShow each light for 1 second.“Loop” forever.6Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems II‘C’ program for traffic light controllerint main() { int r = 1, y = 0, g = 0; /* light off/on */ while (1) { printf("r=%i\ny=%i\ng=%i\n\n", r, y, g); sleep(1); }}% ./trafficr=1y=0g=0r=1y=0g=0r=1y=0g=0r=1y=0g=07Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems II‘C’ program for traffic light controllerint main() { int r = 1, y = 0, g = 0; /* light off/on */ while (1) { printf("r=%i\ny=%i\ng=%i\n\n", r, y, g); sleep(1); }} int next_r, next_y, next_g; /* extra state */ next_r = y; next_y = g; next_g = r; r = next_r; y = next_y; g = next_g; % ./trafficr=1y=0g=0r=0y=0g=1r=0y=1g=0r=1y=0g=0r=0y=0g=1Compute the “next” state for the traffic light.Make the “next” state the “current” state of the traffic light.8Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIint main() { int r = 1, y = 0, g = 0; /* light off/on */ while (1) { printf("r=%i\ny=%i\ng=%i\n\n", r, y, g); sleep(1); }} int next_r, next_y, next_g; /* extra state */ next_r = y; next_y = g; next_g = r; r = next_r; y = next_y; g = next_g; A few observations ...Code would still work if these statements executed simultaneously.Code would still work if these statements executed simultaneously.Wouldn’t it be great if we could group “current” and “next” variables with an abstraction?Sleep(1) sets “time constant”, not C instruction execution rate.A direct digital hardware implementation addresses all of these issues!9Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems II Clock waveform takes the role of sleep(1)!"#$%&'())* ++,!-.)'/ 012-)34$5$%&67&1'8!"#$%&'( )#*#&&'&+,-+.'*/#&+0-12'*,'*3+#45+! ,/$'60&7"89+:+,/$'6$;"9+:+,/$'6.',;%95+! #0&7"8:+#$;":+#.',;%0&7fT1 Hz 1 s1 MHz1 μs1 GHz1 nsAll state changes happen on leading edge of our 1 Hz clock ... thus, lights will switch once per second.1 second (posedge to posedge)10Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIr & next_r? One edge-triggered D flip-flopD QCLKValue of D is sampled on positive clock edge.Q outputs sampled value for rest of cycle.DQPositive-edge sampling makes it easy to think about state.11Thursday, January 28, 2010Spring 2010 EECS150 lec04-SDS-review2Page Flip-flop Timing Waveforms?•Edge-triggered d-type flip-flop–This one is “positive edge-triggered”•“On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored.”•Example waveforms:1212Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIUse 3 Flip-Flops to represent state ...D QD QD QR G YR Y G1 0 0 R Y G0 0 1 R Y G0 1 0 Power up to red state13Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIUse 3 Flip-Flops to represent state ...D QD QD QR G Y“One-Hot Encoding”: State machines where exactly one D flip-flop is in the “1” state at a time (forbidden states: RYG = 000, 011, 101, 110, 111).R Y G1 0 0 R Y G0 0 1 R Y G0 1 0 Power up to red state14Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems II“Simplified” traffic light controllerR Y G1 0 0 R Y G0 0 1 R Y G0 1 0 Power up to red stateNext State Combinational LogicD QD QD QR G Y“Simplified???”: We assume the state at the beginning of time is RYG == 100. A “complete” implementation would include “power up” logic.15Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIInside the combinational logic box ...R Y G1 0 0 R Y G0 0 1 R Y G0 1 0 Power up to red stateNext State Combinational LogicD QD QD QR G YLet’s revisit our original C code ...16Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIint main() { int r = 1, y = 0, g = 0; /* light off/on */ while (1) { printf("r=%i\ny=%i\ng=%i\n\n", r, y, g); sleep(1); }} int next_r, next_y, next_g; /* extra state */ next_r = y; next_y = g; next_g = r; r = next_r; y = next_y; g = next_g; Recall: A few observations ...6 C variables, but only 3 flip-flops. How does that work? 17Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIFlip-flops have an internal output delay ...D QCLKDQt_clk-to-QValue of D is sampled on positive clock edge.Q changes t_clk_to_Q seconds after the positive edge happens (t_clk_to_Q > 0).18Thursday, January 28, 2010UC Regents Spr 2010 © UCBEECS 150 - L4: Synch Systems IIAnd so, even this circuit “works” ...CLKDQt_clk-to-QD QCLKValue of D is sampled on positive clock edge.t_inv = 0Assume inverter has no delay ! (real-world inverters


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Berkeley COMPSCI 150 - Synchronous Digital Systems Review (Part II)

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