FSMs in Verilog and other random thingsFSM structurePowerPoint PresentationSlide 4Slide 5Slide 6Slide 7Non-blockingBlockingFSMs in Verilog and other random things9/27/02FSM structureCLKSTATENextStateLogicInputsOutput LogicOutputsRedYellow Greenchange=1change=1change=1module trafficLightFSM(clk,reset,change,red,yellow,green); input clk,reset,change;output red,yellow,green;reg red,yellow,green;reg [1:0] curState,nextState;parameter showRed = 2’b00, showYellow = 2’b01;parameter showGreen = 2’b10;// state registeralways @(posedge clk)if (reset==1’b1) curState <= 2’b0;else curState <= nextState;// next state logic// dependent only on the current state and inputalways @(curState or change) beginnextState = showRed; // default statecase (curState)showRed: if (change) nextState=showGreen; showYellow: if (change) nextState=showRed; else nextState=showYellow;showGreen: if (change) nextState=showYellow; else nextState=showGreen;endcaseend// Output Logic: dependent ONLY on statealways @(curState) begin// *ALWAYS* put default output valuesred=1’b0; green=1’b0; yellow=1’b0;case (curState)showRed: red=1’b1;showYellow: yellow=1’b1;showGreen: green=1’b1;endcaseendendmoduleEdge DetectorOUTINa bcclkinaboutcNon-blockingalways @(posedge clk)beginE <= ~A;C <= ~E;endAECBlockingalways @(posedge clk)beginE = ~A;C =
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