1Spring 2003 EECS150 - Lec09-review1Page 1EECS150 - Digital DesignLecture 9 – Review 1February 18, 2003John WawrzynekSpring 2003 EECS150 - Lec09-review1Page 2Outline• Announcements/reminders• List of exam topics• Detailed discussion of quizzes and homework assignmentsPlease ask questions throughout!2Spring 2003 EECS150 - Lec09-review1Page 3Announcements/Reminders• Exam 1 this Friday 2/21, 5pm, 1 Pimentel– ~90 minutes of relatively short questions covering the full range of topics from lectures 1-8.– Closed book and notes– Homework and quiz problems are typical• Posted:– Exam 1 from Fall 2003 (Wawrzynek)– Quiz solutions, homework solutions (not including this weeks)– List of potential exam topics• TA exam review this Thursday 2/20, 7pm, 10 EvansSpring 2003 EECS150 - Lec09-review1Page 4Exam TopicsLecture 1 (Intro)Design constraints:performance (speed)cost (complexity)power (energy dissipation)Example systems optimized for each of these.The idea of a design tradeoffs between constraints.Examples of hierarchical representations of digital systems. Benefits of using hierarchy.3Spring 2003 EECS150 - Lec09-review1Page 5Lecture 2 (CMOS)Basic characteristics of ICs and PC boards.Moore's Law.Rough classification of ICs.Qualitative operation of CMOS nFETs and pFETS.Structure of basic logic gates, tri-state buffers, data latches, and edge-triggered flip-flops at the transistor. Operation of these circuitsmodeling transistors as switches.Basic operation of D-type flip-flops in the context of shifters and related circuits.Spring 2003 EECS150 - Lec09-review1Page 6Lecture 3 (FPGAs)High-level structure of FPGAs.Why use FPGAs and their relationship to other types of ICs.The structure of an ideal CLB and LUT.The LUT as a general function block.Mapping circuits to CLBs/LUTs.4Spring 2003 EECS150 - Lec09-review1Page 7Lecture 4 (bool1)Relationship among true-tables, gate diagrams, and Booleanequations. How to convert from one to the other.Design of a ripple adder.Basic axioms of Boolean algebra. Application of theorems of Boolean algebra to algebraic simplification and proving equivalence.Relationship between DeMorgan's law and NAND and NOR gates.Spring 2003 EECS150 - Lec09-review1Page 8Lecture 5 (bool2)Generating canonical forms from TTs.Applying K-maps to simplify SOPs and POSs expressions (including don't cares).Simple factoring to form multi-level logic circuits. Analysis of logic circuits for transistor count (and delay).5Spring 2003 EECS150 - Lec09-review1Page 9Lecture 6 (hdl1)Definition of a netlist. Different forms.A few basic concepts, and constructs of Verilog. Difference between structural and behavioral descriptions. Dataflow description of Boolean expressions.Spring 2003 EECS150 - Lec09-review1Page 10Lecture 7 (fsm1)Formal design process for Moore style FSMs:Translating from English language problem description to state transition diagram (STD).STD to state transition table (STT).STT to logic equations for next state and outputs.Circuit implementation with combinational logic and flip-flops.Motivation for one-hot encoding FSMs.One-hot encoded FSM circuit derivation directly from STT.6Spring 2003 EECS150 - Lec09-review1Page 11Lecture 8 (synthesis)Understanding of the techniques used by logic synthesis tools to convertHDLs to circuits.Blocking and non-blocking procedural assignments.Specification of don't cares in combinational logic.Conceptual and practical understanding of the issue related to accidental latch generation when synthesizing combinational logic.Sequential logic and FSM specification.The topics in this lecture should have taken on much more meaning for you now, given your experience in the lab. I will expect that given aVerilog module, you can derive the synthesized circuit, and likewise, given a circuit you can derive a Verilog
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